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HML/D1H= HRL/D1H= HWLz/DH= D1HKS/D1H= HK0/D1H= HK/H=q D1HI.D1H=J HI.D1H=' HI.D1H= HI.D1H= HIb.DH= D1HH;.D1H= HH.D1H=w HH-sH=Y D1HhG-D1H=2 HxG-D1H= H}G-D1H= HGj-D1H= HGJ-DH= D1H8F#-D1H= HHF-D1H=_ HMF,[H=A D1HE,D1H= HE,D1H= HEu,D1H= HER,D1H= HE2,DH= D1HC ,D1H=j HC+A̾1H=F HC+EDH=) D1HC+D1H= H C+A̾1H= HCb+DH= D1HB;+D1H= H+H=y D1HA*A̾1H=Q HA*PH=9 E1H HM*E1H= AH H*E1H= AH HEX*DH= H HA1.*Eľ1H= H H\ *@H=i E1H eH})E1H=; AH `H)E1H= AH XHE)DH= H WHA1^)Eľ1H= H EH9)@H= D1H)D1H=r H(D1H=R H(DH=1 H1(A̾1H= H( DH= D1Hk(D1H= HH(A̾1H= H*(DH= D1Hh(D1H=b Hh'D1H=B Hp'DH=! Hw1'A̾1H= H'DH= D1H(['D1H= H0;'D1H= H8'DH=y H?1&sH=Y D1H&D1H=2 H&D1H= H&DH= H1p&A̾1H= HR&DH= D1HX+&D1H= HX &D1H=j Hh%DH=I Hw1%A̾1H=& H%%DH= D1H%D1H= Hc%D1H= H@%DH= H1 %A̾1H=~ H%}DH=a D1H@$D1H=: HH$D1H= HX$DH= Hg1x$A̾1H= HwZ$DH= D1H3$D1H= H$D1H=r H#DH=Q H1#A̾1H=. H#-DH= E1H H%#E1H= AH 'H\#E1H= AH HE0#DH= H HA1#Eľ1H=d H H4"\@H=A D1H"D1H= H("D1H= H8x"DH= HG1X"A̾1H= HW:"DH= D1H"D1H=r H!D1H=R H!DH=1 H1!A̾1H= H! DH= E1H Hd!D1H= HD!D1H= H!!DH= H1!A̾1H=_ H  ^fDH=A D1HP D1H= H` D1H= Hpx DH= H1X A̾1H= H: DH= E1H -H E1H=k AH 0HE1H=C AH 0HEDH= H@1H= D1HsD1H= HPD1H= H-D1H= H D1H=i H'D1H=F H,D1H=# H9D1H= H?D1H= HL_f.H= D1H3D1H= HD1H=r HDH=Q H1A̾1H=. H-DH= D1HhD1H= HpkE1H= AH wHE?DH= H vHA1A̾1H=s HlrfH=Y D1H`E1H=2 AH HD1H= HHDH= H1hA̾1H= HJDH= D1H#E1H= AH H-E1H=Z AH H5EDH=5 H HAA1Eľ1H= H HH= D1H[E1H= AH He3E1H= AH HmEDH=m H HyA1Eľ1H=; H H 3H= D1HD1H= HsD1H= HPEľ1H= H H~+fDH= E1H HE1H=[ AH HE1H=3 AH HEDH= H HA1~Eľ1H= H HY@H= D1H83DH= HB1A̾1H=q HRpH=Y D1HD1H=2 HD1H= HDH= H1pA̾1H= H'RDH= D1H`+D1H= Hh D1H=j HxDH=I H1A̾1H=& H%DH= D1HD1H= HcD1H= H@DH= H1 A̾1H=~ H}DH=a D1H@D1H=: HHD1H= HXDH= Hg1xA̾1H= HwZDH= D1H3D1H= HD1H=r HDH=Q H1A̾1H=. H-DH= D1H D1H= H(kD1H= H8HDH= HG1(A̾1H= HW DH=i D1HD1H=B HD1H=" HDH= H1A̾1H= HǾbDH= D1H;A̾1H= HH=y D1H0D1H=O H0KH=1 D1HD1H= HfDH= D1H0cD1H= H0CfDH= D1HD1H=z HD1H=W H D1H=4 HD1H= HD1H= H$lD1H= H)IE1H= AH HgADH=~ H1D1H=Y HD1H=6 H D1H= HD1H= HnD1H= HKD1H= H(D1H= HH=i D1H D1H=B H D1H=" H DH= H1A̾1H= H'bH= D1H@D1H= HD1H=| HD1H=V HRH=; D1HnD1H= HjD1H= HfrD1H= HOD1H= H,D1H= H H=m D1HD1H=C H,??H=( D1H'A̾1H= HH= D1HbD1H= H/BD1 H= H7H= D1HN D1H=Y H? UH=> D1H A̾1H= H/ H= D1HMx D1H= H]X D1H= Hm5 D1H= Hw H=v D1H D1H=O H D1H=, H D1H= H D1H= Hd D1H= HA D1H= H D1H=} H DH=\ H 1 D1H=7 H  D1H= H D1H= Ho D1H= HL D1H= H!) D1H= H& D1H=e H+ DH=D H21 D1H= H5 D1H= H:z D1H= H?W D1H= HD4 D1H= HI D1H=p HN D1H=M HS DH=, HZ1 #H= D1H D1H= HBc H= D1HA D1H= H D1H=} HD1H=Z HD1H=4 Hz0H= D1HD1H= HpD1H= HMD1H= H*A̾1H= H H=p D1HD1H=I HEH=. D1H:D1H= H7D1H= H1eD1H= H(BD1H= HH= D1HʫD1H=\ H۫D1H=: H6H= D1H6H= D1HwH= D1HUD1H= H{3D1H= HH=w D1H+D1H=P HǩD1H=. H̩*H= D1HZD1H= HmH=ѿ D1HȨKD1H= HШ(H= D1H[D1 H=b H^H=G D1HΧD1H= HΧH= D1HQ|H= D1HZH= D1H=8D1H= H9D1H=w HD1H=T H D1H=1 HD1H= HD1H= HiD1H=Ƚ HFD1H= H#D1H= H~H=g D1HD1H=@ H>D1H= H>D1H= H@xD1H=Լ H=UH= D1H3D1H= H D1H=o H D1H=L H D1H=) H D1H= H D1H= H.aD1 H= H >H= D1H D1H={ H D1H=[ HTD1H=8 HMD1H= H D1H= H pD1H=̺ H MH= D1H+D1H= H D1H=j HD1H=G HD1H=$ HD1H= HD1H=޹ H\D1H= H9D1H= HD1H=r HQnH=W D1HD1H=0 HD1H= HH= D1HpiD1H=ȸ HkID1H= H&D1H= HD1H=b HD1H=? H;H=$ D1HD1H= HI{D1H=ڷ HDXD1H= H5D1H= HH=y D1HD1H=R HD1H=, H`(H= D1HD1 H= H hH=̶ D1HFD1H= H?#H= D1HD1H=` H?D1H=: H?6H= D1HD1H= H?vD1H=յ H?SD1H= H?0D1H= H?H=r D1HD1H=K HD1H=+ H'H= D1HD1H= HhD1H=Ǵ HHH= D1H&D1H= H~H=g D1H~D1H== H9H=" D1HD1H= H|DH=ݳ H1\H= D1HG:H= D1HH=| D1HD1H=U HQD1H=5 HD1H= H?D1H= HmD1H=̲ HJD1H= H'D1H= HD1H=c HyD1H== H9H=" D1HD1H= H?yD1H=ձ H?VH= D1Hq4D1H= H:D1H=m H5iH=R D1HպD1H=( H$H= D1H,D1H= H,dD1H=ð H.AH= D1HD1H={ HwH=` D1HD1H=9 HPD1H= HD1H= HtD1H=ӯ HQDH= H11鬿H= D1HD1H=n HD1H=N HLD1H=+ HD1H= HH= D1HAdD1H=î HIAD1H= HND1H=z HSvH=_ D1HD1H=5 H1H= D1HD1H= HqH=խ D1H<OD1H= HD,D1H= HR D1H=e H&aH=J D1HD1H=# HD1H= HD1H= H^ټH=¬ D1HAD1H=r H8D1H=I HȳEH=. D1H]D1H= H]H= D1Hc޶H=Ǧ D1HAD1H= H!霶H= D1H,zH=c D1HD1H=< H8H=! D1H`H= D1HyD1H=إ HYԵH= D1H7D1H= HD1H=v HD1H=S HD1H=0 HD1H= HD1H= HްhD1H=Ǥ HְED1H= Hz"D1H= HD1H=_ H[H=D D1H 9H=" D1HH= D1HzD1H=٣ HZD1H= H?7D1H= HpD1H=s HD1H=P HD1H=- HA̾1H= HH= E1H HldD1H=â H`DEľ1H= H ۃHr隲H= D1HZxH=a E1H ͂HukE1H=3 AH ЂHEľ1H= H ˂HH= D1H!eA̾1H=á HG±H= E1H wHjE1H=} AH rH(E1H=U AH rH0EDH=0 H yH<A1A̾1H= H#H= D1H`D1H= H=D1H= HD1H=y HD1H=V HRH=; D1Hr~D1H= Hz~D1H= H~rDH=ӟ H~1RA̾1H= H~4鯯H= D1H}D1H=q H}DH=X H BHdA1Eľ1H=& H .HH= D1HD1H=ݞ H^ٮH=ž D1HD1 H= H 閬H= D1HD1H=X HD1H=5 HD1H= H D1H= H mD1H=̛ H JD1H= H 'D1H= H D1H=d H `H=I D1H@D1H=" HHD1 H= HPH= D1Hc^D1H= Hk>A̾1H= Hu 雪H= D1HD1H=] HD1H=: HD1H= HD1H= HrD1H=љ HOD1H= H,E1H= AH H4UADH=a H1E1H=< A H HAD1 H= Hn H= D1HlD1H=˘ HLA̾1H= H.驨H= D1H D1H=h HdH=M D1HD1H=& H$A̾1H= H6H= D1HDgD1H=Ɨ HLGA̾1H= HV)餧H= D1HD1H=f H%D1H=C H%D1H= H%D1H= H%{E1H=ږ AH 2HGAOD1H= H%/骦H= D1HB! D1H=l HJ!D1H=L HR!D1H=) HW!?D1H= H\!D1H= HY!aD1H= H^!>D1H= Hk!D1H=z Hp!E1H=W AH t!HQAD1H=+ Hi!D1H= Hn!D1H= H{!cD1H=” H!@D1H= H!D1H=| H!D1H=Y H!D1H=6 H!D1H= H!D1H= H!nD1H=͓ H!LD1H= H!,駣H= D1H D1H=i HD1H=I HD1H=& HD1H= HD1H= H^^D1H= H;D1H= HD1H=w HD1H=T HD1H=1 HD1H= HD1H= HiD1H=ȑ HFD1H= H#D1H= H:D1H=_ HD1H=< HD1H= HD1H= HtD1H=Ӑ HܠRD1H= HԠ2魠H= D1H[D1H=o HD1H=L H D1H=) HD1H= HD1H= HaD1H= H>D1H= H#DH=| H*1D1H=W H5D1H=4 HBD1H= HGD1H= HTlD1H=ˎ HQ?ID1H= H&D1H= H3DH=d H;1D1H=@ H6 AH HGAE1AH= H YHnAH= D1HeA̾1H=Ê HGšH= D1HB%A̾1H= HL邚H=k D1H: D1H=D HB D1H=! HG D1H= HL |D1H=ۉ HQ \יH= D1H :D1H= H D1H=v H D1H=S H D1H=0 H ,H= D1HT D1H= H\ lD1H=ˈ Ha ID1H= Hf &D1H= Hk 遘H=j D1HD1H=C HD1H= HD1H= H{D1H=ڇ H[֗H= D1Hn9D1H= HvD1H=u H{D1H=R HD1H=/ H+H= D1H{D1H= HkH=φ D1HID1H= H&D1H= HD1H=b H^H=G D1HD1H= HH= D1HD1H=ޅ H\D1H= H <鷕H= D1HD1H=y H'D1H=S H,OH=8 D1HgD1H= HoH= D1HjD1H=Ʉ HGD1H= H,$D1H= H9D1H=` HFD1H== HSD1H= H`D1H= HmuDH=փ H|1RD1H= H/D1H= H D1H=k HD1H=H HD1H=% HD1H= HD1H=߂ H^D1H= H>鹒H= D1HD1H={ HD1H=X HD1H=5 HD1H= HD1H= HmD1H=́ HJD1H= H'DH= H1D1H=c HD1H=@ HD1H= HD1H= HxD1H=׀ H UD1H= H2D1H= HDH=p H&1D1H=K H*D1H=) H/%H= D1HD1H= HeeD1H= HjBD1H= HoD1H=~ HtD1H=[ HyD1H=8 H~D1H= HDH=~ H1pD1H=~ HMD1H=~ H*D1H=~ HD1H=f~ HD1H=C~ HD1H= ~ HD1H=} H{DH=} H1XD1H=} H6D1H=} H鑍H=z} D1HD1H=P} HLH=5} D1HD1H=} HD1H=| HiD1H=| HIČH=| D1H'D1H=| HD1H=c| HD1H=@| H?H5E1H=Tl AH HͱE1H=,l AH HE衱DH=l H HA1wEľ1H=k H vHR{H=k E1H J>H4)E1H=k AH ZH3E1H=`k AH OH;EհDH=;k H KHGA1諰Eľ1H= k H 6Hق膰{H=j E1H V=H3]E1H=j AH Hg5E1H=j AH HoE DH=oj H H{A1߯Eľ1H==j H H 躯5zH=j E1H b<H23葯E1H=i AH چHiE1H=i AH φHE=DH=i H ˆHA1Eľ1H=qi H HAiyH=Ri E1H n;Hf2ŮE1H=$i AH Hρ蝮E1H=h AH HׁEqDH=h H HA1GEľ1H=h H vHu"xH=h E1H 9H1D1H=Xh H9٭D1H=8h H9趭DH=h H91薭A̾1H=g H9xwH=g E1H 8H0OE1H=g AH HY'E1H=g AH HaEDH=ag H HmA1ѬEľ1H=/g H H~謬'wH=g E1H 7H$0胬E1H=f AH pH[E1H=f AH eHE/DH=f H aHA1Eľ1H=cf H LH3~[vH=Df E1H 7HX/跫E1H=f AH 0H~菫E1H=e AH %H~EcDH=e H !H~A19Eľ1H=e H Hg}uH=xe E1H 6H.E1H=Je AH H}êE1H="e AH H}E藪DH=d H H ~A1mEľ1H=d H H|HtH=d E1H 5H-E1H=~d AH ~H)}E1H=Vd AH ~H1}E˩DH=1d H ~H=}A1衩Eľ1H=c H ~H{|sH=c E1H 3H,SE1H=c AH 3H]|+E1H=c AH 3He|EDH=ec H 3Hq|A1ըEľ1H=3c H 3H{谨+sH=c E1H 2H(,臨D1H=b H{gD1H=b H{DDH=b H {1$A̾1H=b H{rH=jb E1H 1H~+ݧD1H=` Hux迥D1H=` Hmx蜥DH=_ Hdx1|A̾1H=_ H\x^oH=_ D1H-I H_輎D1H=I H_虎YH=H D1HwD1H=H H$TXH=H D1Hw2D1H=H H_D1H=kH HdgXH=PH D1HʍD1H=)H H觍D1H=H H脍WH=G D1HbD1H=G H?WH=G D1H2D1H=yG HBuWH=^G D1H،D1H=7G H]赌D1H=G Hy]蒌D1H=F HgoVH=F D1HMD1H=F H*D1H=F HVH=kF D1HD1H=AF H‹=VH=&F D1H蠋D1H=E H[}D1H=E H[ZD1H=E H7D1H=E HD1H=sE H[D1H=PE H[ΊD1H=-E Hs諊A̾1H= E Hr荊UH=D D1HhkD1H=D HkZHD1H=D HaZ%D1H=D H+~TH=gD D1HnD1H=@D Hv軉D1H=D Hp蘉D1H=C HYuSH=C D1H SD1H=C H(0D1H=C H- D1H=lC H*D1 H=FC H/LjBSH=+C D1H襈D1H=C H肈D1H=B HX_D1H=B H? H„=OH=&? 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fo)D$0fo)D$@fo)D$PfoВ#foHD$0rHD$8)$fo)D$fo)D$ HD$pf)D$@)D$P)D$`fo)$fo)D$8f.fo)$fo)D$fo)D$ fo)D$0xfoX)$f)D$fDfo()$f)D$fDfo)$fo)D$foϐ)D$ ffoX)$fo)D$fo)D$ fXfohHD$le 2)$+fDfo8)$f)D$fDHQSFP281fH$HT$)D$Dfo)$foԏ)D$f.fo)$fo)D$ffH$CXPHD$)D$HQSFP+kfH$QSFPHD$)D$SHDWDM-SFP;fH$X2HD$)D$#fH$XPAKHD$)D$HXFP-EfH$XFFHD$)D$fH$XFPHD$)D$HXENPAKfoh)$f)D$fDfH$SFPHD$)D$cfo)$fo )D$@ffH$GBICHD$)D$#fo)$fo)D$fo)D$ flff.AWfAVIAUAATEeUSHxdH%(HD$h1ID$`L)$)D$)D$ )D$0)D$@)D$PnuzH=rUtL5iLDLL=mL%#Et/@H=9UHtHGLIE1sLM$H=TDu1LH5K{ EthL%E{L-cL5Xt%uz,LL1Θuۃt} L1H誘f.H=CTHD$hdH+%(uwHx[]A\A]A^A_D,LL1T\ L1H-LH5Hz1yXATIUHSHdH%(HD$1Y1HLHSH$HE:u6HH  HT$dH+%(uH[]A\øĔ@ATUSHdH%(HD$1HtNHIē1HHHnu'H$:uL9wHT$dH+%(uH[]A\G8vfATUHSLg@HI<$?u;I|$?ountCH5.pu@1Ek8HC@[]A\[1]A\f1DtH RH=x^ifAVIAUAATEUSHQH5@HEE1ɹH)DLHA)薔x#HJHHH)u[]A\A]A^fDAUAATIUHSH蒕HH0MD9s7HRM$M$Mt^LH5w1XAL$Md$@H5w1E121HALH[]A\A]H5lw1H5Qw11fDMH=~PH[H-]1A\A]ѕ*uGuuXƆHN0HtH/w%HRtу uƆfƆHN0HuƆ1U*SHHLGXH?LIh8FK8uoIxRt*Ll*Ht H[]D{PoHH5ED$ D$ H[]@HC@H=OHhH1wH[]덐AU1ɺ+ATUHSHH_XLHLfHORLc8s$HCpHE@+Ml$HE8LLCltH[]A\A]DHUE11ɾLE111HH5y@duAD$HWH1蟃]]fUIHwXH?'Hn8ujA@8u21ɺ'Hnx@HH5]f.I@@H==H1WH1]]fAU1ɺ(ATUSHHHoXLHLNC8HS@Le8LEH ?@HMpu$HMl$(LAEKTHE1LE111HH5)nAEx^AD$x@HH5]f.I@@H=u;HUH1π]]fU$SHHHwXH?C8uNHn81ɺ$Hx%{P H5HD$ D$ H[]fDHC@H=:HATH1H[]fAU1ɺ%ATUSHHHoXLHLNC8HS@Le8LEH =HMpu$HMl$%LAEKTHE1L-E111HH5d%kAEx^AD$E11LL課uu{PmH5H~D$ D$ H[]A]A^fDHC@H=8HQH1o}H[]A]A^밸f.UIHwXH?Hn8NujA@8u21ɺ.H.x@HH5]f.I@@H=e7HPH1|]]fAU1ɺ/ATUHSHH_XLHLH]Lc8s$HCpHE@/Ml$HE8LLCHUE11ɾLE11ҹHH5!hxaAD$ %u) Key is too short for device (%u < %u) Cannot set RX flow hash configurationCannot get current device settingsDriver supports one or more unknown flags Cannot get current wake-on-lan settingsCannot set new wake-on-lan settingsCannot allocate memory for register dumpMagic number 0x%08x does not match 0x%08x Hex and raw dump cannot be specified togetherCannot get module EEPROM informationCannot allocate memory for Module EEPROM dataThe sub commands will be applied to all %d queues Queue %d, no coalesce parameters changed Cannot set device per queue parametersThe subcommand is not supported yet-k|--show-features|--show-offload|-K|--features|--offload--show-priv-flags|--set-priv-flags-l|--show-channels|-L|--set-channels-c|--show-coalesce|-C|--coalesceDisplay standard information about device [ speed %d ] [ lanes %d ] [ duplex half|full ] [ port tp|aui|bnc|mii|fibre|da ] [ mdix auto|on|off ] [ autoneg on|off ] [ advertise %x[/%x] | mode on|off ... [--] ] [ phyad %d ] [ xcvr internal|external ] [ wol %d[/%d] | p|u|m|b|a|g|s|f|d... ] [ sopass %x:%x:%x:%x:%x:%x ] [ msglvl %d[/%d] | type on|off ... [--] ] [ master-slave preferred-master|preferred-slave|forced-master|forced-slave ] [ --src aggregate | emac | pmac ] [ autoneg on|off ] [ rx on|off ] [ tx on|off ] [adaptive-rx on|off] [adaptive-tx on|off] [rx-usecs N] [rx-frames N] [rx-usecs-irq N] [rx-frames-irq N] [tx-usecs N] [tx-frames N] [tx-usecs-irq N] [tx-frames-irq N] [stats-block-usecs N] [pkt-rate-low N] [rx-usecs-low N] [rx-frames-low N] [tx-usecs-low N] [tx-frames-low N] [pkt-rate-high N] [rx-usecs-high N] [rx-frames-high N] [tx-usecs-high N] [tx-frames-high N] [sample-interval N] [cqe-mode-rx on|off] [cqe-mode-tx on|off] [tx-aggr-max-bytes N] [tx-aggr-max-frames N] [tx-aggr-time-usecs N] [ rx N ] [ rx-mini N ] [ rx-jumbo N ] [ tx N ] [ rx-buf-len N ] [ tcp-data-split auto|on|off ] [ cqe-size N ] [ tx-push on|off ] [ rx-push on|off ] [ tx-push-buf-len N] [ hds-thresh N ] -k|--show-features|--show-offloadGet state of protocol offload and other featuresSet protocol offload and other features [ raw on|off ] [ file FILENAME ] [ raw on|off ] [ offset N ] [ length N ] [ magic N ] [ offset N ] [ length N ] [ value N ] Show visible port identification (e.g. blinking) [ online | offline | external_lb ] [ --all-groups | --groups [eth-phy] [eth-mac] [eth-ctrl] [rmon] ] [ --src aggregate | emac | pmac ] -n|-u|--show-nfc|--show-ntupleShow Rx network flow classification options or rules [ rx-flow-hash tcp4|udp4|ah4|esp4|sctp4|gtpc4|gtpc4t|gtpu4|gtpu4e|gtpu4u|gtpu4d|tcp6|udp6|ah6|esp6|sctp6|gtpc6|gtpc6t|gtpu6|gtpu6e|gtpu6u|gtpu6d [context %d] | rule %d ] -N|-U|--config-nfc|--config-ntupleConfigure Rx network flow classification options or rules rx-flow-hash tcp4|udp4|ah4|esp4|sctp4|gtpc4|gtpc4t|gtpu4|gtpu4e|gtpu4u|gtpu4d|tcp6|udp6|ah6|esp6|sctp6|gtpc6|gtpc6t|gtpu6|gtpu6e|gtpu6u|gtpu6d m|v|t|s|d|f|n|r|e... [context %d] | flow-type ether|ip4|tcp4|udp4|sctp4|ah4|esp4|ip6|tcp6|udp6|ah6|esp6|sctp6 [ src %x:%x:%x:%x:%x:%x [m %x:%x:%x:%x:%x:%x] ] [ dst %x:%x:%x:%x:%x:%x [m %x:%x:%x:%x:%x:%x] ] [ proto %d [m %x] ] [ src-ip IP-ADDRESS [m IP-ADDRESS] ] [ dst-ip IP-ADDRESS [m IP-ADDRESS] ] [ tos %d [m %x] ] [ tclass %d [m %x] ] [ l4proto %d [m %x] ] [ src-port %d [m %x] ] [ dst-port %d [m %x] ] [ spi %d [m %x] ] [ vlan-etype %x [m %x] ] [ vlan %x [m %x] ] [ user-def %x [m %x] ] [ dst-mac %x:%x:%x:%x:%x:%x [m %x:%x:%x:%x:%x:%x] ] [ action %d ] | [ vf %d queue %d ] [ context %d ] [ loc %d ] | delete %d Show time stamping capabilities [ index N qualifier precise|approx ] Get selected hardware time stamping-x|--show-rxfh-indir|--show-rxfhShow Rx flow hash indirection table and/or RSS hash keySet Rx flow hash indirection table and/or RSS hash key [ context %d|new ] [ equal N | weight W0 W1 ... | default ] [ hkey %x:%x:%x:%x:%x:.... ] [ hfunc FUNC ] [ xfrm symmetric-xor | symmetric-or-xor | none ] [ delete ] Flash firmware image from the specified file to a region on the device FILENAME [ REGION-NUMBER-TO-FLASH ] Show permanent hardware address [ rx N ] [ tx N ] [ other N ] [ combined N ] -m|--dump-module-eeprom|--module-infoQuery/Decode Module EEPROM information and optical diagnostics if available [ raw on|off ] [ hex on|off ] [ offset N ] [ length N ] [ page N ] [ bank N ] [ i2c N ] [ eee on|off ] [ advertise %x ] [ tx-lpi on|off ] [ tx-timer %d ] [ downshift on|off [count N] ] [ fast-link-down on|off [msecs N] ] [ energy-detect-power-down on|off [msecs N] ] [ downshift ] [ fast-link-down ] [ energy-detect-power-down ] [ rx-copybreak ] [ tx-copybreak ] [ tx-buf-size ] [ pfc-prevention-tout ] [ rx-copybreak N ] [ tx-copybreak N ] [ tx-buf-size N ] [ pfc-prevention-tout N ] [ flags %x ] [ mgmt ] [ mgmt-shared ] [ irq ] [ irq-shared ] [ dma ] [ dma-shared ] [ filter ] [ filter-shared ] [ offload ] [ offload-shared ] [ mac ] [ mac-shared ] [ phy ] [ phy-shared ] [ ram ] [ ram-shared ] [ ap ] [ ap-shared ] [ dedicated ] [ all ] [ encoding auto|off|rs|baser|llrs [...] ] The supported sub commands include --show-coalesce, --coalesce [queue_mask %x] SUB_COMMAND Print cable test time domain reflectrometery data [ first N ] [ last N ] [ step N ] [ pair N ] Show NIC tunnel offload informationShow transceiver module settingsSet transceiver module settings [ power-mode-policy high|auto ] [ enable on|off ] [ node-id N ] [ node-cnt N ] [ to-tmr N ] [ burst-cnt N ] [ burst-tmr N ] Set MAC merge layer parameters [ verify-enabled on|off ] [ verify-time N ] [ tx-enabled on|off ] [ pmac-enabled on|off ] [ tx-min-frag-size 60-252 ] Show settings for Power Sourcing EquipmentSet Power Sourcing Equipment settings [ podl-pse-admin-control enable|disable ] [ c33-pse-admin-control enable|disable ] [ c33-pse-avail-pw-limit N ] Flash transceiver module firmwarenone (HWTSTAMP_FILTER_NONE)all (HWTSTAMP_FILTER_ALL)some (HWTSTAMP_FILTER_SOME)ptpv1-l4-event (HWTSTAMP_FILTER_PTP_V1_L4_EVENT)ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)ntp-all (HWTSTAMP_FILTER_NTP_ALL)off (HWTSTAMP_TX_OFF)on (HWTSTAMP_TX_ON)one-step-sync (HWTSTAMP_TX_ONESTEP_SYNC)hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)software-system-clock (SOF_TIMESTAMPING_SOFTWARE)hardware-legacy-clock (SOF_TIMESTAMPING_SYS_HARDWARE)hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)QxQXQ8QQPpZ`ZPZ^^^^^^@Z0Z^^^ ZZZ^YgHhgUgf[feYedjieihhjSnmm:mljjl'lkk?kjwvkyxxyyy}xxx}x}xwwwwwwzzz{zYz7zzyIy'yyx `@8=8QQ3.QQQQQ)QQ$QQQStoppedDisabledYesNo10Mbits/ Sec100Mbits/SecDescriptor Registers Command Registers Interrupt Registers Link status Register ValidInvalidMDI MDI-X Unknown normalbiglittle10Mb/s100Mb/s1000Mb/snot usedno link config64-bit32-bit100MHzPCI-X66MHzPCI133MHzdon't passignoredacceptignore1/21/41/8reserved163848192409620481024512256M88IGPIGP2unknownUp0-5050-8080-110110-140140+reverse5-bitMIIforce MDIforce MDIX1000 auto, 10/100 MDIwtfPCI ExpressPHY Registers JAGCore Global Registers TXDMA Registers RXDMA Registers pausedSERDESundefined0x%04lx: %-16s 0x%08x hash_table_highhash_table_lowr_des_startx_des_startr_buff_sizeecntrlieventimaskivecr_des_activex_des_activemii_datamii_speedr_boundr_fstartx_fstartfun_coder_cntrlr_hashx_cntrl%s: 0x%x %s Counter overflow No missed frames %u missed frames DiagnosticStandardRound-robinRX-has-priorityBigLittlefailRxOKTxNoBufs TxOK FD_Short AUI_TP RxTimeout RxStopped RxNoBufs TxUnder TxJabber TxStop HashPerfectdis Hash-only Filtering Pass Bad Frames Inverse Filtering Promisc Mode Pass All Multicast Forcing collisions Back pressure enabled Capture effect enabled Transmit interrupt Transmit stopped Transmit underflow Receive interrupt Receive stopped AUI_TP pin Full duplex Link fail System error AUITP Autopolarity state PLL self-test done PLL self-test pass PLL sampler low PLL sampler high SIA reset CSR autoconfiguration 10base-T APLL start Input enable Enable pins 1, 3 Enable pins 2, 4 Enable pins 5, 6, 7 Encoder enable Loopback enable Driver enable Link pulse send enable Receive squelch enable Heartbeat enable Link test enable Autopolarity enable Set polarity plus Jabber disable Host unjab Jabber clock Test clock Force unsquelch Force link fail PLL self-test start Force receiver low EarlyRx TimerExp ANC Link pass Timer expired ExtReg SROM BootROM Read Mode Continuous mode Unstable NLP detected Transmit remote fault AUI/BNC port10base-T port Must Be One Autonegotiation enable BNC GP LED1 enable GP LED1 on LED stretch disable GP LED2 enable GP LED2 on 21040 Registers 21041 Registers %s: 0x%x Reg 0x%x: 0x%x Filter: %d Rule Type: TCP over IPv4 Rule Type: UDP over IPv4 Rule Type: SCTP over IPv4 SPI: %d mask: 0x%x Rule Type: Raw IPv4 Rule Type: TCP over IPv6 Rule Type: UDP over IPv6 Rule Type: SCTP over IPv6 Rule Type: Raw IPv6 Unknown Flow type: %d Action: Drop Action: Wake-on-LAN (queue base offset: %llu)\t\n\r\f\b\\\"\'10 Mbps100 Mbps1000 MbpsReserved?Not forcedDrop On LockDrop On UnlockDrop to CPUUnmodifiedUntaggedTaggedNormalProviderEther Type DSADefaultsTag PriorityTag & IP PriorityNo unknown DANo unknown multicast DANo unknown unicast DAAllow unknown DABlocking/ListeningForwarding152210240FallbackCheckPort Status%.02u: %-38.38s 0x%.4x Pause Enabled %-36.36s %u My PauseHalf-duplex Flow Control802.3 PHY DetectedLink Status %-36.36s %s Auto-Media Detect DisableTransmitter PausedConfig DuplexConfig Mode %-36.36s 0x%x PCS ControlFlow Control's Forced valueForce Flow ControlLink's Forced valueForce LinkDuplex's Forced valueForce DuplexForce SpeedJamming ControlSwitch IdentifierPort ControlEgress ModeIngress & Egress Header ModeIGMP and MLD SnoopingFrame ModeVLAN TunnelTagIfBothInitial Priority assignmentEgress Flooding modePort StatePort Control 1Message PortTrunk PortTrunk IDFID[5:4] %-36.36s 0x%.2x Port Base VLAN Map (Header)FID[3:0]VLANTableDefault VLAN ID & PriorityDefault PriorityForce to use Default VIDDefault VLAN IdentifierPort Control 2Force good FCS in the frameJumbo Mode802.1QModeDiscard Tagged FramesDiscard Untagged FramesMap using DA hitsARP Mirror enableEgress Monitor Source PortIngress Monitor Source PortEgress Rate ControlEgress Rate Control 2Port Association VectorPort ATU ControlPriority OverridePortETypeInDiscardsLo Frame CounterInDiscardsHi Frame CounterInFiltered Frame CounterOutFiltered Frame CounterTag Remap 0-3Tag Remap 4-7Queue Counters100 or 200 MbpsDelayDefault200No error, link OKLink failureOfflineAutoneg ErrorNo PauseSymmetric PauseSymmetric & Asymmetric Pause16 Bits24 Bits32 Bits40 Bits100BaseFX1000BaseXSGMII SystemSGMII MediaFalseTrue14mV700mV112mV210mV308mV406mV504mV602mVEEE EnabledPhysical ControlRGMII Receive Timing ControlRGMII Transmit Timing Control200 BASE ModeFID[11:4] %-36.36s 0x%.3x Use Default Queue PriorityPolicy ControlPort Ether TypeRx Frame CounterLED ControlFiber ControlFiber ResetAutoneg EnablePower downIsolateRestart AutonegFiber Status100Base-X FD100Base-X HDAutoneg CompleteRemote FaultPHY ID 1PHY ID 2Fiber Autoneg Advertisement1000BaseX HD1000BaseX FDFiber Link Autoneg AbilityAcknowledgeFiber Autoneg ExpansionPage ReceivedLink Partner Autoneg AbilityFiber Next Page TransmitFiber Link Partner Next PageExtended StatusFiber Specific ControlFiber Transmit FIFO DepthSERDES LoopbackForce Link GoodMAC Interface Power DownFiber Specific StatusSpeed/Duplex ResolvedSyncEnergy DetectTransmit PauseReceive PauseFiber Interrupt EnableSpeed ChangedDuplex ChangedLink Status ChangeSymbol ErrorFalse CarrierFiber Interrupt StatusFiber Receive Error CounterPRBS ControlPRBS Error Counter LSBPRBS Error Counter MSBFiber Specific Control 21000BaseX Noise Filtering1000BaseFX Noise FilteringSERDES Autoneg Bypass EnableSERDES Autoneg Bypass StatusFiber Transmitter DisableSGMII/Fiber Output Amplitude10 Gb or 2500 MbpsAlternate10 9 8 Transmit Pause Enable bitReceive Pause Enable bitDuplex FixedAlternate Speed ModeMII PHY ModeEEE force valueForce EEELAG PortVTU PageLAG IDForce MappingAllow bad FCSAllow VID of ZeroIP Priority Mapping TableIEEE Priority Mapping TablePort Control 3Queue ControlCut Through ControlDebug Counters%s Switch Port Registers 64 bytes128 bytes192 bytes0x%.03x: %-44.44s 0x%.8x MAX_FL (Maximum frame length) %-47.47s %u FCE (Flow control enable)PROM (Promiscuous mode)LOOP (Internal loopback)FDEN (Full duplex enable)HBC (Heartbeat control)GTS (Graceful transmit stop)IADDR1 %-47.47s 0x%.16llx IADDR2 %-47.47s 0x%.16x GADDR1GADDR2X_WMRK %-47.47s %s %-47.47s 0x%.2x Cannot get control socketnetlink disabledioctl-only request--debug--disable-netlink--json--include-statistics--phyinvalid phy indexlistening... Unexpected --phy parameter--monitorrxclass: Unknown flow type RSS hash key:%02x:json_writer.cself->depth > 0truefalseUnknown MDI-X: %s mdi-xmdi-x-auto MDI-X: on (forced) (auto)off (forced) mdi-x-forcedjson objectself->depth == 0 Supports Wake-on: %s supports-wake-on Wake-on: %s secureon-password SecureOn password: %s%02x%luSI mode registerSI control BDR mode registerSI capability register 0SI capability register 1TX BDR 0 mode registerTX BDR 0 status registerTX BDR 0 length registerTX BDR 1 mode registerTX BDR 1 status registerTX BDR 1 length registerTX BDR 2 mode registerTX BDR 2 status registerTX BDR 2 length registerTX BDR 3 mode registerTX BDR 3 status registerTX BDR 3 length registerTX BDR 4 mode registerTX BDR 4 status registerTX BDR 4 length registerTX BDR 5 mode registerTX BDR 5 status registerTX BDR 5 length registerTX BDR 6 mode registerTX BDR 6 status registerTX BDR 6 length registerTX BDR 7 mode registerTX BDR 7 status registerTX BDR 7 length registerTX BDR 8 mode registerTX BDR 8 status registerTX BDR 8 length registerTX BDR 9 mode registerTX BDR 9 status registerTX BDR 9 length registerTX BDR 10 mode registerTX BDR 10 status registerTX BDR 10 length registerTX BDR 11 mode registerTX BDR 11 status registerTX BDR 11 length registerTX BDR 12 mode registerTX BDR 12 status registerTX BDR 12 length registerTX BDR 13 mode registerTX BDR 13 status registerTX BDR 13 length registerTX BDR 14 mode registerTX BDR 14 status registerTX BDR 14 length registerTX BDR 15 mode registerTX BDR 15 status registerTX BDR 15 length registerRX BDR 0 mode registerRX BDR 0 status registerRX BDR 0 buffer size registerRX BDR 0 length registerRX BDR 1 mode registerRX BDR 1 status registerRX BDR 1 buffer size registerRX BDR 1 length registerRX BDR 2 mode registerRX BDR 2 status registerRX BDR 2 buffer size registerRX BDR 2 length registerRX BDR 3 mode registerRX BDR 3 status registerRX BDR 3 buffer size registerRX BDR 3 length registerRX BDR 4 mode registerRX BDR 4 status registerRX BDR 4 buffer size registerRX BDR 4 length registerRX BDR 5 mode registerRX BDR 5 status registerRX BDR 5 buffer size registerRX BDR 5 length registerRX BDR 6 mode registerRX BDR 6 status registerRX BDR 6 buffer size registerRX BDR 6 length registerRX BDR 7 mode registerRX BDR 7 status registerRX BDR 7 buffer size registerRX BDR 7 length registerRX BDR 8 mode registerRX BDR 8 status registerRX BDR 8 buffer size registerRX BDR 8 length registerRX BDR 9 mode registerRX BDR 9 status registerRX BDR 9 buffer size registerRX BDR 9 length registerRX BDR 10 mode registerRX BDR 10 status registerRX BDR 10 length registerRX BDR 11 mode registerRX BDR 11 status registerRX BDR 11 length registerRX BDR 12 mode registerRX BDR 12 status registerRX BDR 12 length registerRX BDR 13 mode registerRX BDR 13 status registerRX BDR 13 length registerRX BDR 14 mode registerRX BDR 14 status registerRX BDR 14 length registerRX BDR 15 mode registerRX BDR 15 status registerRX BDR 15 length registerPort mode registerPort status registerPort capability register 0Port capability register 1Port RFS capability register88E6085 88E6095 88E6097 88E6190X88E6390X88E6131 88E6320 88E6123 88E6161 88E6165 88E6171 88E6172 88E6175 88E6176 88E6190 88E6191 88E6185 88E6240 88E6290 88E6321 88E6141 88E6341 88E6352 88E6350 88E6351 88E6390 Compensation Disabled ModeHigh Power ModeNormal Compensation ModeAutonegotiation disableTransmit disableAbility detectAcknowledge detectComplete acknowledgeFLP link good, nway completeLink checkunknown (reserved)internal loopbackexternal loopbackunknown (not used) Bus error: parity Bus error: master abort Bus error: target abortstoppedrunning: fetch descrunning: wait xmit endrunning: read bufrunning: setup packetsuspendedrunning: close descrunning: chk pkt endrunning: wait for pktrunning: closerunning: flushrunning: queueNo transmit automatic polling8-longword boundary alignment0x00100: Transmit descriptor base address register %08X 0x00140: Transmit descriptor length register 0x%08X 0x00120: Receive descriptor base address register %08X 0x00150: Receive descriptor length register 0x%08X 0x00048: Command 0 register 0x%08X Interrupts: %s Device: %s 0x00050: Command 2 register 0x%08X Promiscuous mode: %s Retransmit on underflow: %s 0x00054: Command 3 register 0x%08X Jumbo frame: %s Admit only VLAN frame: %s Delete VLAN tag: %s 0x00064: Command 7 register 0x%08X 0x00038: Interrupt register 0x%08X Any interrupt is set: %s Link change interrupt: %s Register 0 auto-poll interrupt: %s Transmit interrupt: %s Software timer interrupt: %s Receive interrupt: %s 0x00040: Interrupt enable register 0x%08X Link change interrupt: %s Register 0 auto-poll interrupt: %s Transmit interrupt: %s Software timer interrupt: %s Receive interrupt: %s Logical Address Filter Register 0x00168: Logical address filter register 0x%08X%08X 0x00030: Link status register 0x%08X Link status: %s Auto negotiation complete %s Duplex %s Speed %s 0x00030: Link status register 0x%08X Link status: %s SCB Status Word (Lower Word) 0x%04X RU Status: Idle RU Status: Suspended RU Status: No Resources RU Status: Ready RU Status: Suspended with no more RBDs RU Status: No Resources due to no more RBDs RU Status: Ready with no RBDs present RU Status: Unknown State CU Status: Idle CU Status: Suspended CU Status: Active CU Status: Unknown State ---- Interrupts Pending ---- Flow Control Pause: %s Early Receive: %s Software Generated Interrupt: %s MDI Done: %s RU Not In Ready State: %s CU Not in Active State: %s RU Received Frame: %s CU Completed Command: %s SCB Command Word (Upper Word) 0x%04X RU Command: No Command RU Command: RU Start RU Command: RU Resume RU Command: RU Abort RU Command: Load RU Base RU Command: Unknown CU Command: No Command CU Command: CU Start CU Command: CU Resume CU Command: Load Dump Counters Address CU Command: Dump Counters CU Command: Load CU Base CU Command: Dump & Reset Counters CU Command: Unknown Software Generated Interrupt: %s ---- Interrupts Masked ---- ALL Interrupts: %s Flow Control Pause: %s Early Receive: %s RU Not In Ready State: %s CU Not in Active State: %s RU Received Frame: %s CU Completed Command: %s MDI/MDI-X Status: 0x00000: CTRL (Device control register) 0x%08X Endian mode (buffers): %s Link reset: %s Set link up: %s Invert Loss-Of-Signal: %s Receive flow control: %s Transmit flow control: %s VLAN mode: %s Auto speed detect: %s Speed select: %s Force speed: %s Force duplex: %s 0x00008: STATUS (Device status register) 0x%08X Duplex: %s Link up: %s TBI mode: %s Link speed: %s Bus type: %s Port number: %s TBI mode: %s Link speed: %s Bus type: %s Bus speed: %s Bus width: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Long packet: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Canonical form indicator: %s Discard pause frames: %s Pass MAC control frames: %s Receive buffer size: %s 0x02808: RDLEN (Receive desc length) 0x%08X 0x02810: RDH (Receive desc head) 0x%08X 0x02818: RDT (Receive desc tail) 0x%08X 0x02820: RDTR (Receive delay timer) 0x%08X 0x00400: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s Pad short packets: %s Software XOFF Transmission: %s Re-transmit on late collision: %s 0x03808: TDLEN (Transmit desc length) 0x%08X 0x03810: TDH (Transmit desc head) 0x%08X 0x03818: TDT (Transmit desc tail) 0x%08X 0x03820: TIDV (Transmit delay timer) 0x%08X PHY type: %s M88 PHY STATUS REGISTER: 0x%08X Jabber: %s Polarity: %s Downshifted: %s MDI/MDIX: %s Cable Length Estimate: %s meters Link State: %s Speed & Duplex Resolved: %s Page Received: %s Duplex: %s Speed: %s mbps M88 PHY CONTROL REGISTER: 0x%08X Jabber function: %s Auto-polarity: %s SQE Test: %s CLK125: %s Auto-MDIX: %s Extended 10Base-T Distance: %s 100Base-TX Interface: %s Scrambler: %s Force Link Good: %s Assert CRS on Transmit: %s 0x0, Basic Control Reg = 0x%04X 0x1, Basic Status Reg = 0x%04X 0x2, PHY identifier 1 = 0x%04X 0x3, PHY identifier 2 = 0x%04X 0x4, Auto Neg Advertisement = 0x%04X 0x5, Auto Neg L Partner Ability = 0x%04X 0x6, Auto Neg Expansion = 0x%04X 0x7, Reserved = 0x%04X 0x8, Reserved = 0x%04X 0x9, 1000T Control = 0x%04X 0xA, 1000T Status = 0x%04X 0xB, Reserved = 0x%04X 0xC, Reserved = 0x%04X 0xD, MMD Access Control = 0x%04X 0xE, MMD access Data = 0x%04X 0xF, Extended Status = 0x%04X 0x10, Phy Index = 0x%04X 0x11, Phy Data = 0x%04X 0x12, MPhy Control = 0x%04X 0x13, Phy Loopback Control1 = 0x%04X 0x14, Phy Loopback Control2 = 0x%04X 0x15, Register Management = 0x%04X 0x16, Phy Config = 0x%04X 0x17, Phy Phy Control = 0x%04X 0x18, Phy Interrupt Mask = 0x%04X 0x19, Phy Interrupt Status = 0x%04X 0x1A, Phy Phy Status = 0x%04X 0x1B, Phy LED1 = 0x%04X 0x1C, Phy LED2 = 0x%04X 0x0, TXQ Start Address = 0x%04X 0x1, TXQ End Address = 0x%04X 0x2, RXQ Start Address = 0x%04X 0x3, RXQ End Address = 0x%04X 0x4, Power Management Status = 0x%04X 0x5, Interrupt Status = 0x%04X 0x6, Interrupt Mask = 0x%04X 0x7, Int Alias Clear Mask = 0x%04X 0x8, Int Status Alias = 0x%04X 0x9, Software Reset = 0x%04X 0xA, SLV Timer = 0x%04X 0xB, MSI Config = 0x%04X 0xC, Loopback = 0x%04X 0xD, Watchdog Timer = 0x%04X 0x0, Control Status = 0x%04X 0x1, Packet Ring Base Addr (Hi) = 0x%04X 0x2, Packet Ring Base Addr (Lo) = 0x%04X 0x3, Packet Ring Num Descrs = 0x%04X 0x4, TX Queue Write Address = 0x%04X 0x5, TX Queue Write Address Ext = 0x%04X 0x6, TX Queue Read Address = 0x%04X 0x7, Status Writeback Addr (Hi) = 0x%04X 0x8, Status Writeback Addr (Lo) = 0x%04X 0x9, Service Request = 0x%04X 0xA, Service Complete = 0x%04X 0xB, Cache Read Index = 0x%04X 0xC, Cache Write Index = 0x%04X 0xD, TXDMA Error = 0x%04X 0xE, Descriptor Abort Count = 0x%04X 0xF, Payload Abort Count = 0x%04X 0x10, Writeback Abort Count = 0x%04X 0x11, Descriptor Timeout Count = 0x%04X 0x12, Payload Timeout Count = 0x%04X 0x13, Writeback Timeout Count = 0x%04X 0x14, Descriptor Error Count = 0x%04X 0x15, Payload Error Count = 0x%04X 0x16, Writeback Error Count = 0x%04X 0x17, Dropped TLP Count = 0x%04X 0x18, New service Complete = 0x%04X 0x1A, Ethernet Packet Count = 0x%04X 0x1, Writeback Addr (Hi) = 0x%04X 0x2, Writeback Addr (Lo) = 0x%04X 0x3, Num Packets Done = 0x%04X 0x4, Max Packet Time = 0x%04X 0x5, RX Queue Read Addr = 0x%04X 0x6, RX Queue Read Address Ext = 0x%04X 0x7, RX Queue Write Addr = 0x%04X 0x8, Packet Ring Base Addr (Hi) = 0x%04X 0x9, Packet Ring Base Addr (Lo) = 0x%04X 0xA, Packet Ring Num Descrs = 0x%04X 0xE, Packet Ring Avail Offset = 0x%04X 0xF, Packet Ring Full Offset = 0x%04X 0x10, Packet Ring Access Index = 0x%04X 0x11, Packet Ring Min Descrip = 0x%04X 0x12, FBR0 Address (Lo) = 0x%04X 0x13, FBR0 Address (Hi) = 0x%04X 0x14, FBR0 Num Descriptors = 0x%04X 0x15, FBR0 Available Offset = 0x%04X 0x16, FBR0 Full Offset = 0x%04X 0x17, FBR0 Read Index = 0x%04X 0x18, FBR0 Minimum Descriptors = 0x%04X 0x19, FBR1 Address (Lo) = 0x%04X 0x1A, FBR1 Address (Hi) = 0x%04X 0x1B, FBR1 Num Descriptors = 0x%04X 0x1C, FBR1 Available Offset = 0x%04X 0x1D, FBR1 Full Offset = 0x%04X 0x1E, FBR1 Read Index = 0x%04X 0x1F, FBR1 Minimum Descriptors = 0x%04X 0x00000: CTRL (Device control register) 0x%08X Invert Loss-Of-Signal: %s Receive flow control: %s Transmit flow control: %s VLAN mode: %s Set link up: %s D3COLD WakeUp capability advertisement: %s Auto speed detect: %s Speed select: %s Force speed: %s Force duplex: %s 0x00008: STATUS (Device status register) 0x%08X Duplex: %s Link up: %s Transmission: %s DMA clock gating: %s TBI mode: %s Link speed: %s Bus type: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Long packet: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Cononical form indicator: %s Discard pause frames: %s Pass MAC control frames: %s Loopback mode: %s Receive buffer size: %s 0x02808: RDLEN (Receive desc length) 0x%08X 0x02810: RDH (Receive desc head) 0x%08X 0x02818: RDT (Receive desc tail) 0x%08X 0x00400: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s Pad short packets: %s Software XOFF Transmission: %s Re-transmit on late collision: %s 0x03808: TDLEN (Transmit desc length) 0x%08X 0x03810: TDH (Transmit desc head) 0x%08X 0x03818: TDT (Transmit desc tail) 0x%08X 0x00018: CTRL_EXT (Extended device control) 0x%08X 0x00018: MDIC (MDI control) 0x%08X 0x00024: SCTL (SERDES ANA) 0x%08X 0x00034: CONNSW (Copper/Fiber switch control) 0x%08X 0x00038: VET (VLAN Ether type) 0x%08X 0x00E00: LEDCTL (LED control) 0x%08X 0x01000: PBA (Packet buffer allocation) 0x%08X 0x01008: PBS (Packet buffer size) 0x%08X 0x01048: FRTIMER (Free running timer) 0x%08X 0x0104C: TCPTIMER (TCP timer) 0x%08X 0x00010: EEC (EEPROM/FLASH control) 0x%08X 0x01580: EICR (Extended interrupt cause) 0x%08X 0x01520: EICS (Extended interrupt cause set) 0x%08X 0x01524: EIMS (Extended interrup set/read) 0x%08X 0x01528: EIMC (Extended interrupt mask clear) 0x%08X 0x0152C: EIAC (Extended interrupt auto clear) 0x%08X 0x01530: EIAM (Extended interrupt auto mask) 0x%08X 0x01500: ICR (Interrupt cause read) 0x%08X 0x01504: ICS (Interrupt cause set) 0x%08X 0x01508: IMS (Interrupt mask set/read) 0x%08X 0x0150C: IMC (Interrupt mask clear) 0x%08X 0x04100: IAC (Interrupt assertion count) 0x%08X 0x01510: IAM (Interr acknowledge auto-mask) 0x%08X 0x05AC0: IMIRVP (Immed interr rx VLAN priority) 0x%08X 0x00028: FCAL (Flow control address low) 0x%08X 0x0002C: FCAH (Flow control address high) 0x%08X 0x00170: FCTTV (Flow control tx timer value) 0x%08X 0x02160: FCRTL (Flow control rx threshold low) 0x%08X 0x02168: FCRTH (Flow control rx threshold high) 0x%08X 0x02460: FCRTV (Flow control refresh threshold) 0x%08X 0x05000: RXCSUM (Receive checksum control) 0x%08X 0x05004: RLPML (Receive long packet max length) 0x%08X 0x05008: RFCTL (Receive filter control) 0x%08X 0x05818: MRQC (Multiple rx queues command) 0x%08X 0x0581C: VMD_CTL (VMDq control) 0x%08X 0x00404: TCTL_EXT (Transmit control extended) 0x%08X 0x00410: TIPG (Transmit IPG) 0x%08X 0x03590: DTXCTL (DMA tx control) 0x%08X 0x05800: WUC (Wake up control) 0x%08X 0x05808: WUFC (Wake up filter control) 0x%08X 0x05810: WUS (Wake up status) 0x%08X 0x05838: IPAV (IP address valid) 0x%08X 0x05900: WUPL (Wake up packet length) 0x%08X 0x04200: PCS_CFG (PCS configuration 0) 0x%08X 0x04208: PCS_LCTL (PCS link control) 0x%08X 0x0420C: PCS_LSTS (PCS link status) 0x%08X 0x04218: PCS_ANADV (AN advertisement) 0x%08X 0x0421C: PCS_LPAB (Link partner ability) 0x%08X 0x04220: PCS_NPTX (Next Page transmit) 0x%08X 0x04224: PCS_LPABNP (Link partner ability Next Page) 0x%08X 0x04000: CRCERRS (CRC error count) 0x%08X 0x04004: ALGNERRC (Alignment error count) 0x%08X 0x04008: SYMERRS (Symbol error count) 0x%08X 0x0400C: RXERRC (RX error count) 0x%08X 0x04010: MPC (Missed packets count) 0x%08X 0x04014: SCC (Single collision count) 0x%08X 0x04018: ECOL (Excessive collisions count) 0x%08X 0x0401C: MCC (Multiple collision count) 0x%08X 0x04020: LATECOL (Late collisions count) 0x%08X 0x04028: COLC (Collision count) 0x%08X 0x04030: DC (Defer count) 0x%08X 0x04034: TNCRS (Transmit with no CRS) 0x%08X 0x04038: SEC (Sequence error count) 0x%08X 0x0403C: HTDPMC (Host tx discrd pkts MAC count) 0x%08X 0x04040: RLEC (Receive length error count) 0x%08X 0x04048: XONRXC (XON received count) 0x%08X 0x0404C: XONTXC (XON transmitted count) 0x%08X 0x04050: XOFFRXC (XOFF received count) 0x%08X 0x04054: XOFFTXC (XOFF transmitted count) 0x%08X 0x04058: FCRUC (FC received unsupported count) 0x%08X 0x0405C: PRC64 (Packets rx (64 B) count) 0x%08X 0x04060: PRC127 (Packets rx (65-127 B) count) 0x%08X 0x04064: PRC255 (Packets rx (128-255 B) count) 0x%08X 0x04068: PRC511 (Packets rx (256-511 B) count) 0x%08X 0x0406C: PRC1023 (Packets rx (512-1023 B) count) 0x%08X 0x04070: PRC1522 (Packets rx (1024-max B) count) 0x%08X 0x04074: GPRC (Good packets received count) 0x%08X 0x04078: BPRC (Broadcast packets rx count) 0x%08X 0x0407C: MPRC (Multicast packets rx count) 0x%08X 0x04080: GPTC (Good packets tx count) 0x%08X 0x04088: GORCL (Good octets rx count lower) 0x%08X 0x0408C: GORCH (Good octets rx count upper) 0x%08X 0x04090: GOTCL (Good octets tx count lower) 0x%08X 0x04094: GOTCH (Good octets tx count upper) 0x%08X 0x040A0: RNBC (Receive no buffers count) 0x%08X 0x040A4: RUC (Receive undersize count) 0x%08X 0x040A8: RFC (Receive fragment count) 0x%08X 0x040AC: ROC (Receive oversize count) 0x%08X 0x040B0: RJC (Receive jabber count) 0x%08X 0x040B4: MGPRC (Management packets rx count) 0x%08X 0x040B8: MGPDC (Management pkts dropped count) 0x%08X 0x040BC: MGPTC (Management packets tx count) 0x%08X 0x040C0: TORL (Total octets received lower) 0x%08X 0x040C4: TORH (Total octets received upper) 0x%08X 0x040C8: TOTL (Total octets transmitted lower) 0x%08X 0x040CC: TOTH (Total octets transmitted upper) 0x%08X 0x040D0: TPR (Total packets received) 0x%08X 0x040D4: TPT (Total packets transmitted) 0x%08X 0x040D8: PTC64 (Packets tx (64 B) count) 0x%08X 0x040DC: PTC127 (Packets tx (65-127 B) count) 0x%08X 0x040E0: PTC255 (Packets tx (128-255 B) count) 0x%08X 0x040E4: PTC511 (Packets tx (256-511 B) count) 0x%08X 0x040E8: PTC1023 (Packets tx (512-1023 B) count) 0x%08X 0x040EC: PTC1522 (Packets tx (> 1024 B) count) 0x%08X 0x040F0: MPTC (Multicast packets tx count) 0x%08X 0x040F4: BPTC (Broadcast packets tx count) 0x%08X 0x040F8: TSCTC (TCP segment context tx count) 0x%08X 0x04104: RPTHC (Rx packets to host count) 0x%08X 0x04118: HGPTC (Host good packets tx count) 0x%08X 0x04128: HGORCL (Host good octets rx cnt lower) 0x%08X 0x0412C: HGORCH (Host good octets rx cnt upper) 0x%08X 0x04130: HGOTCL (Host good octets tx cnt lower) 0x%08X 0x04134: HGOTCH (Host good octets tx cnt upper) 0x%08X 0x04138: LENNERS (Length error count) 0x%08X 0x04228: SCVPC (SerDes/SGMII code viol pkt cnt) 0x%08X 0x0A018: HRMPC (Header redir missed pkt count) 0x%08X 0x0%02X: SRRCTL%d (Split and replic rx ctl%d) 0x%08X 0x0%02X: PSRTYPE%d (Packet split receive type%d) 0x%08X 0x0%02X: RDBAL%d (Rx desc base addr low%d) 0x%08X 0x0%02X: RDBAH%d (Rx desc base addr high%d) 0x%08X 0x0%02X: RDLEN%d (Rx descriptor length%d) 0x%08X 0x0%02X: RDH%d (Rx descriptor head%d) 0x%08X 0x0%02X: RDT%d (Rx descriptor tail%d) 0x%08X 0x0%02X: RXDCTL%d (Rx descriptor control%d) 0x%08X 0x0%02X: EITR%d (Interrupt throttle%d) 0x%08X 0x0%02X: IMIR%d (Immediate interrupt Rx%d) 0x%08X 0x0%02X: IMIREXT%d (Immediate interr Rx extended%d) 0x%08X 0x0%02X: RAL%02d (Receive address low%02d) 0x%08X 0x0%02X: RAH%02d (Receive address high%02d) 0x%08X 0x0%02X: TDBAL%d (Tx desc base address low%d) 0x%08X 0x0%02X: TDBAH%d (Tx desc base address high%d) 0x%08X 0x0%02X: TDLEN%d (Tx descriptor length%d) 0x%08X 0x0%02X: TDH%d (Transmit descriptor head%d) 0x%08X 0x0%02X: TDT%d (Transmit descriptor tail%d) 0x%08X 0x0%02X: TXDCTL%d (Transmit descriptor control%d) 0x%08X 0x0%02X: TDWBAL%d (Tx desc complete wb addr low%d) 0x%08X 0x0%02X: TDWBAH%d (Tx desc complete wb addr hi%d) 0x%08X 0x0%02X: DCA_TXCTRL%d (Tx DCA control%d) 0x%08X 0x0%02X: IP4AT%d (IPv4 address table%d) 0x%08X 0x0%02X: IP6AT%d (IPv6 address table%d) 0x%08X 0x0%02X: WUPM%02d (Wake up packet memory%02d) 0x%08X 0x0%02X: FFMT%03d (Flexible filter mask table%03d) 0x%08X 0x0%02X: FFVT%03d (Flexible filter value table%03d) 0x%08X 0x0%02X: FFLT%d (Flexible filter length table%d) 0x%08X 0x03410: TDFH (Tx data FIFO head) 0x%08X 0x03418: TDFT (Tx data FIFO tail) 0x%08X 0x03420: TDFHS (Tx data FIFO head saved) 0x%08X 0x03430: TDFPC (Tx data FIFO packet count) 0x%08X 0x05BF4: RR2DCDELAY (Max. DMA read delay) 0x%08X 0x40: CSR8 (Missed Frames Counter) 0x%08x Start/Stop Backoff Counter Flaky oscillator disable Transmit buffer unavailable Transmit jabber timeout Receive buffer unavailable Receive watchdog timeout Abnormal interrupt summary Normal interrupt summary Network connection error AUI_TP pin autoconfiguration SIA PLL external input enable Encoder input multiplexer Serial interface input multiplexer Collision squelch enable Collision detect enable Receive watchdog disable Receive watchdog release Special capture effect enabled Early receive interrupt Selected port receive activity Non-selected port receive activity Link partner negotiable SIA register reset asserted CSR autoconfiguration enabled 10base-T/AUI autosensing 0x00: CSR0 (Bus Mode) 0x%08x %s %s address space Cache alignment: %s Programmable burst length unlimited Programmable burst length %d longwords %s endian data buffers Descriptor skip length %d longwords %s bus arbitration scheme Software reset asserted 0x18: CSR3 (Rx Ring Base Address) 0x%08x 0x20: CSR4 (Tx Ring Base Address) 0x%08x 0x28: CSR5 (Status) 0x%08x %s Transmit process %s Receive process %s Link %s Normal interrupts: %s%s%s Abnormal intr: %s%s%s%s%s%s%s%s 0x30: CSR6 (Operating Mode) 0x%08x %s%s Transmit threshold %d bytes Transmit DMA %sabled %s Operating mode: %s %s duplex %s%s%s%s%s%s%s Receive DMA %sabled %s filtering mode 0x38: CSR7 (Interrupt Mask) 0x%08x %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s0x48: CSR9 (Ethernet Address ROM) 0x%08x 0x58: CSR11 (Full Duplex Autoconfig) 0x%08x 0x60: CSR12 (SIA Status) 0x%08x %s%s%s%s%s%s%s AUI_TP pin: %s 0x68: CSR13 (SIA Connectivity) 0x%08x %s%s%s%s External port output multiplexer select: %u%u%u%u %s%s%s%s %s interface selected %s%s%s0x70: CSR14 (SIA Transmit and Receive) 0x%08x %s%s%s%s%s%s%s %s %s%s%s%s0x78: CSR15 (SIA General) 0x%08x %s%s%s%s%s%s%s%s%s%s0x00: CSR0 (Bus Mode) 0x%08x %s endian descriptors %s %s address space Cache alignment: %s Normal interrupts: %s%s%s%s%s Abnormal intr: %s%s%s%s%s%s%s 0x38: CSR7 (Interrupt Mask) 0x%08x %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s0x48: CSR9 (Boot and Ethernet ROMs) 0x%08x Select bits: %s%s%s%s%s%s Data: %d%d%d%d%d%d%d%d 0x50: CSR10 (Boot ROM Address) 0x%08x 0x58: CSR11 (General Purpose Timer) 0x%08x %s Timer value: %u cycles 0x60: CSR12 (SIA Status) 0x%08x Link partner code word 0x%04x %s NWay state: %s %s%s%s%s%s%s%s%s%s%s%s0x68: CSR13 (SIA Connectivity) 0x%08x SIA Diagnostic Mode 0x%04x %s %s%s0x70: CSR14 (SIA Transmit and Receive) 0x%08x %s%s%s%s%s%s%s%s%s%s %s %s%s%s%s0x78: CSR15 (SIA General) 0x%08x %s%s%s%s%s%s%s%s%s%s%s%s %s port selected %s%s%sExpected length to be multiple of 8 bytes Src IP addr: %s mask: %s Dest IP addr: %s mask: %s TOS: 0x%x mask: 0x%x Src IP addr: %s mask: %s Dest IP addr: %s mask: %s Traffic Class: 0x%x mask: 0x%x Src port: %d mask: 0x%x Dest port: %d mask: 0x%x Rule Type: IPSEC AH over IPv4 Rule Type: IPSEC ESP over IPv4 Protocol: %d mask: 0x%x L4 bytes: 0x%x mask: 0x%x Rule Type: IPSEC AH over IPv6 Rule Type: IPSEC ESP over IPv6 Flow Type: Raw Ethernet Src MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X Dest MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X Ethertype: 0x%X mask: 0x%X VLAN EtherType: 0x%x mask: 0x%x VLAN: 0x%x mask: 0x%x User-defined: 0x%llx mask: 0x%llx Dest MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X Action: Direct to RSS Context %u Action: Direct to VF %llu queue %llu Action: Direct to queue %llu Source Address Filtering controls %-36.36s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s InFiltered/TcamCtr Frame CounterLink Partner Next Page Ability------------------------------ %s Switch Port SERDES Registers -------------------------------------RCR (Receive Control Register)BC_REJ (Broadcast frame reject)DRT (Disable receive on transmit)TCR (Transmit Control Register)RFC_PAUSE (Receive frame control pause)TFC_PAUSE (Transmit frame control pause)IAUR (Individual Address Upper Register)IALR (Individual Address Lower Register)GAUR (Group Address Upper Register)GALR (Group Address Lower Register)TFWR (Transmit FIFO Watermark Register)FRBR (FIFO Receive Bound Register)R_BOUND (Highest valid FIFO RAM address)EMRBR (Maximum Receive Buffer Size)R_BUF_SIZE (Receive buffer size) MG %d RXSTP %d REG_LOWP_RXETY %d TX_LOWP_ENA %d SFD %d NO_LEN_CHK %d SEND_IDLE %d CNT_FRM_EN %d SWR %d TXP %d XGLP %d TX_ADDR_INS %d PAUSE_IGN %d PAUSE_FWD %d CRC %d PAD %d PROMIS %d WAN %d RX_EN %d TX_EN %d At least one weight must be non-zero Total weight exceeds the size of the indirection table Device name longer than %u characters ethtool netlink support for subcommand missingnetlink interface initialization failedsubcommand does not support wildcard dumpkernel netlink support for subcommand missing--phy parameters expects a phy indexNetlink interface initialization failed, option --monitor not supported. multicast group 'monitor' not found monitoring for option '%s' not supported JSON output not available for this subcommanddevice name '%s' longer than %u characters %s, subcommand not supported by ioctl %s, wildcard dump not supported %s, device name longer than %u not supported rxclass: Cannot get RX class ruleIPV4_USER_FLOW with wrong ip_ver SI primary MAC address register 0SI primary MAC address register 1SI control BDR status registerSI control BDR base address register 0SI control BDR base address register 1SI control BDR producer index registerSI control BDR consumer index registerSI control BDR length registerSI uncorrectable error frame drop count registerTX BDR 0 base address register 0TX BDR 0 base address register 1TX BDR 0 producer index registerTX BDR 0 consumer index registerTX BDR 0 interrupt enable registerTX BDR 0 interrupt coalescing register 0TX BDR 0 interrupt coalescing register 1TX BDR 1 base address register 0TX BDR 1 base address register 1TX BDR 1 producer index registerTX BDR 1 consumer index registerTX BDR 1 interrupt enable registerTX BDR 1 interrupt coalescing register 0TX BDR 1 interrupt coalescing register 1TX BDR 2 base address register 0TX BDR 2 base address register 1TX BDR 2 producer index registerTX BDR 2 consumer index registerTX BDR 2 interrupt enable registerTX BDR 2 interrupt coalescing register 0TX BDR 2 interrupt coalescing register 1TX BDR 3 base address register 0TX BDR 3 base address register 1TX BDR 3 producer index registerTX BDR 3 consumer index registerTX BDR 3 interrupt enable registerTX BDR 3 interrupt coalescing register 0TX BDR 3 interrupt coalescing register 1TX BDR 4 base address register 0TX BDR 4 base address register 1TX BDR 4 producer index registerTX BDR 4 consumer index registerTX BDR 4 interrupt enable registerTX BDR 4 interrupt coalescing register 0TX BDR 4 interrupt coalescing register 1TX BDR 5 base address register 0TX BDR 5 base address register 1TX BDR 5 producer index registerTX BDR 5 consumer index registerTX BDR 5 interrupt enable registerTX BDR 5 interrupt coalescing register 0TX BDR 5 interrupt coalescing register 1TX BDR 6 base address register 0TX BDR 6 base address register 1TX BDR 6 producer index registerTX BDR 6 consumer index registerTX BDR 6 interrupt enable registerTX BDR 6 interrupt coalescing register 0TX BDR 6 interrupt coalescing register 1TX BDR 7 base address register 0TX BDR 7 base address register 1TX BDR 7 producer index registerTX BDR 7 consumer index registerTX BDR 7 interrupt enable registerTX BDR 7 interrupt coalescing register 0TX BDR 7 interrupt coalescing register 1TX BDR 8 base address register 0TX BDR 8 base address register 1TX BDR 8 producer index registerTX BDR 8 consumer index registerTX BDR 8 interrupt enable registerTX BDR 8 interrupt coalescing register 0TX BDR 8 interrupt coalescing register 1TX BDR 9 base address register 0TX BDR 9 base address register 1TX BDR 9 producer index registerTX BDR 9 consumer index registerTX BDR 9 interrupt enable registerTX BDR 9 interrupt coalescing register 0TX BDR 9 interrupt coalescing register 1TX BDR 10 base address register 0TX BDR 10 base address register 1TX BDR 10 producer index registerTX BDR 10 consumer index registerTX BDR 10 interrupt enable registerTX BDR 10 interrupt coalescing register 0TX BDR 10 interrupt coalescing register 1TX BDR 11 base address register 0TX BDR 11 base address register 1TX BDR 11 producer index registerTX BDR 11 consumer index registerTX BDR 11 interrupt enable registerTX BDR 11 interrupt coalescing register 0TX BDR 11 interrupt coalescing register 1TX BDR 12 base address register 0TX BDR 12 base address register 1TX BDR 12 producer index registerTX BDR 12 consumer index registerTX BDR 12 interrupt enable registerTX BDR 12 interrupt coalescing register 0TX BDR 12 interrupt coalescing register 1TX BDR 13 base address register 0TX BDR 13 base address register 1TX BDR 13 producer index registerTX BDR 13 consumer index registerTX BDR 13 interrupt enable registerTX BDR 13 interrupt coalescing register 0TX BDR 13 interrupt coalescing register 1TX BDR 14 base address register 0TX BDR 14 base address register 1TX BDR 14 producer index registerTX BDR 14 consumer index registerTX BDR 14 interrupt enable registerTX BDR 14 interrupt coalescing register 0TX BDR 14 interrupt coalescing register 1TX BDR 15 base address register 0TX BDR 15 base address register 1TX BDR 15 producer index registerTX BDR 15 consumer index registerTX BDR 15 interrupt enable registerTX BDR 15 interrupt coalescing register 0TX BDR 15 interrupt coalescing register 1RX BDR 0 producer index registerRX BDR 0 consumer index registerRX BDR 0 base address register 0RX BDR 0 base address register 1RX BDR 0 interrupt enable registerRX BDR 0 interrupt coalescing register 0RX BDR 0 interrupt coalescing register 1RX BDR 1 producer index registerRX BDR 1 consumer index registerRX BDR 1 base address register 0RX BDR 1 base address register 1RX BDR 1 interrupt enable registerRX BDR 1 interrupt coalescing register 0RX BDR 1 interrupt coalescing register 1RX BDR 2 producer index registerRX BDR 2 consumer index registerRX BDR 2 base address register 0RX BDR 2 base address register 1RX BDR 2 interrupt enable registerRX BDR 2 interrupt coalescing register 0RX BDR 2 interrupt coalescing register 1RX BDR 3 producer index registerRX BDR 3 consumer index registerRX BDR 3 base address register 0RX BDR 3 base address register 1RX BDR 3 interrupt enable registerRX BDR 3 interrupt coalescing register 0RX BDR 3 interrupt coalescing register 1RX BDR 4 producer index registerRX BDR 4 consumer index registerRX BDR 4 base address register 0RX BDR 4 base address register 1RX BDR 4 interrupt enable registerRX BDR 4 interrupt coalescing register 0RX BDR 4 interrupt coalescing register 1RX BDR 5 producer index registerRX BDR 5 consumer index registerRX BDR 5 base address register 0RX BDR 5 base address register 1RX BDR 5 interrupt enable registerRX BDR 5 interrupt coalescing register 0RX BDR 5 interrupt coalescing register 1RX BDR 6 producer index registerRX BDR 6 consumer index registerRX BDR 6 base address register 0RX BDR 6 base address register 1RX BDR 6 interrupt enable registerRX BDR 6 interrupt coalescing register 0RX BDR 6 interrupt coalescing register 1RX BDR 7 producer index registerRX BDR 7 consumer index registerRX BDR 7 base address register 0RX BDR 7 base address register 1RX BDR 7 interrupt enable registerRX BDR 7 interrupt coalescing register 0RX BDR 7 interrupt coalescing register 1RX BDR 8 producer index registerRX BDR 8 consumer index registerRX BDR 8 base address register 0RX BDR 8 base address register 1RX BDR 8 interrupt enable registerRX BDR 8 interrupt coalescing register 0RX BDR 8 interrupt coalescing register 1RX BDR 9 producer index registerRX BDR 9 consumer index registerRX BDR 9 base address register 0RX BDR 9 base address register 1RX BDR 9 interrupt enable registerRX BDR 9 interrupt coalescing register 0RX BDR 9 interrupt coalescing register 1RX BDR 10 buffer size registerRX BDR 10 producer index registerRX BDR 10 consumer index registerRX BDR 10 base address register 0RX BDR 10 base address register 1RX BDR 10 interrupt enable registerRX BDR 10 interrupt coalescing register 0RX BDR 10 interrupt coalescing register 1RX BDR 11 buffer size registerRX BDR 11 producer index registerRX BDR 11 consumer index registerRX BDR 11 base address register 0RX BDR 11 base address register 1RX BDR 11 interrupt enable registerRX BDR 11 interrupt coalescing register 0RX BDR 11 interrupt coalescing register 1RX BDR 12 buffer size registerRX BDR 12 producer index registerRX BDR 12 consumer index registerRX BDR 12 base address register 0RX BDR 12 base address register 1RX BDR 12 interrupt enable registerRX BDR 12 interrupt coalescing register 0RX BDR 12 interrupt coalescing register 1RX BDR 13 buffer size registerRX BDR 13 producer index registerRX BDR 13 consumer index registerRX BDR 13 base address register 0RX BDR 13 base address register 1RX BDR 13 interrupt enable registerRX BDR 13 interrupt coalescing register 0RX BDR 13 interrupt coalescing register 1RX BDR 14 buffer size registerRX BDR 14 producer index registerRX BDR 14 consumer index registerRX BDR 14 base address register 0RX BDR 14 base address register 1RX BDR 14 interrupt enable registerRX BDR 14 interrupt coalescing register 0RX BDR 14 interrupt coalescing register 1RX BDR 15 buffer size registerRX BDR 15 producer index registerRX BDR 15 consumer index registerRX BDR 15 base address register 0RX BDR 15 base address register 1RX BDR 15 interrupt enable registerRX BDR 15 interrupt coalescing register 0RX BDR 15 interrupt coalescing register 1Port SI promiscuous mode registerPort SI0 primary MAC address register 0Port SI0 primary MAC address register 1Port HTA transmit memory buffer allocation registerPort SI0 configuration register 0Port traffic class 0 maximum SDU registerPort eMAC Command and Configuration RegisterPort eMAC Maximum Frame Length RegisterPort eMAC Interface Mode Control Register Bus error: (unknown code, reserved)Transmit automatic polling every 200 secondsTransmit automatic polling every 800 secondsTransmit automatic polling every 1.6 milliseconds16-longword boundary alignment32-longword boundary alignment0 P    p |4@ `!kjjj!kiii!k\l\lll mgm!k!k!kmpppopdpooooooooooooooooooooLpoooo4pzxxxuDudts$r rqqqqpq|qdqTqDqpppp4q$qp q{{{|$|D|d|||||}{{{{$}D}d}}{{{{}} <$ <̇lT<$ }}t\D,}}}}ܑ̒đ}}}}}}̎T<$ ܂Ă~~}ɓ44\Dt\D,444444̔44td       H`jsonw_destroyjsonw_end 123J  !"#$%&'()*+,-./0456789:;<=>?@ABCDEFGHIKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxMAL%d Registers TX| RX| CTP%d = 0x%08x RCBS%d = 0x%08x (%d) EMAC%d Registers IPCR = 0x%08x ZMII%d Registers RGMII%d Registers FER = %08x SSR = %08x TAH%d Registers Driver: %s Version: %s APROM: %04x CSR%02d: BCR%02d: MII%02d: BABL CERR MISS MERR RINT IDON INTR RXON TXON TDMD STOP INIT BABLM MISSM MERRM RINTM TINTM IDONM DXSUFLO LAPPEN DXMT2PD EMBA BSWP EN124 DMAPLUS TXDPOLL APAD_XMT ASTRP_RCV MFCO MFCON UINTCMD UINT RCVCCO RCVCCOM TXSTRT TXSTRTM JAB JABM TOKINTD LTINTEN SINT SINTE SLPINT SLPINTE EXDINT EXDINTE MPPLBA MPINT MPINTE MPEN MPMODE SPND FASTSPNDE RXFRTG RDMD RXDPOLL STINT STINTE MREINT MREINTE MAPINT MAPINTE MCCINT MCCINTE MCCIINT MCCIINTE MIIPDTINT MIIPDTINTE PCnet/PCI 79C970 PCnet/PCI II 79C970A PCnet/FAST 79C971 PCnet/FAST+ 79C972 PCnet/FAST III 79C973 PCnet/Home 79C978 PCnet/FAST III 79C975 PCnet/PRO 79C976VER: %04x PARTIDU: %04x TMAULOOP LEDPE APROMWE INTLEVEL EADISEL AWAKE ASEL XMAUSEL PVALID EEDET %s Init 0x%08X Value 0x%08X MAC AddressesAddr %d %02X%cGenesisYukonYukon-LiteYukon-LPYukon-2 XLYukon ExtremeYukon-2 EC UltraYukon-2 ECYukon-2 FEYukon-2 FE PlusYukon SupremeYukon Ultra 2Yukon Optima(Unknown) (rev %d) %12s address: %02X %02XPhysicalControl RegistersModeration Timer %s Prefetch Control 0x%08X Last Index %u TX1 report %u TX2 report %u TX threshold %u Put Index %u Get Index %u cmd%08x = %08x 10G1GActiveReversedNot DoneNot Half/FullAdvertiseForce10/100In ProgressFailedPassedAcceptedRejectedReverseMaskedBypassedFree-RunningPhase-AdjustedForcedEnhancedReducedFailed or Not RunMac/BIU Registers Reset In Progress Rx Complete %s Interrupt: %s Rx DescriptorRx Packet ErrorRx Early ThresholdRx IdleRx OverrunTx Packet OKTx DescriptorTx Packet ErrorTx IdleTx UnderrunMIB ServiceSoftwarePower Management EventPhyHigh Bits ErrorRx Status FIFO OverrunReceived Target AbortReceived Master AbortSignaled System ErrorDetected Parity ErrorRx Reset CompleteTx Reset Complete No Interrupts Active Interrupts %s Wake on Arp Enabled SecureOn Hack Detected Phy Interrupt Received Arp Received Pattern 0 Received Pattern 1 Received Pattern 2 Received Pattern 3 Received Magic Packet Received Counters Frozen Value = %d Internal Phy Registers ---------------------- Port Isolated Loopback Enabled Remote Fault Detected Advertising 100Base-T4 Advertising Pause Next Page Desired Supports 100Base-T4 Supports Pause Indicates Remote Fault MII Interrupt Detected False Carrier Detected Rx Error Detected MII Interrupts %s MII Interrupt Pending 'Magic' Phy Registers RxErr TxErr RxNoBuf LinkChg RxFIFO TxNoBuf SWInt TimeOut SERR %s%s%s%s%s%s%s%s%s%s%s ERxOK ERxOverWrite ERxBad ERxGood , RESET %s%s%s%s Big-endian mode Home LAN enable VLAN de-tagging RX checksumming PCI 64-bit DAC PCI Multiple RW Offset Value ------ ---------- 0x%04x 0x%08x LAN911x Registers index 1, MAC_CR = 0x%08X index 2, ADDRH = 0x%08X index 3, ADDRL = 0x%08X index 4, HASHH = 0x%08X index 5, HASHL = 0x%08X index 6, MII_ACC = 0x%08X index 7, MII_DATA = 0x%08X index 8, FLOW = 0x%08X index 9, VLAN1 = 0x%08X index A, VLAN2 = 0x%08X index B, WUFF = 0x%08X index C, WUCSR = 0x%08X index 7, Reserved = 0x%04X index 8, Reserved = 0x%04X index 9, Reserved = 0x%04X index 10, Reserved = 0x%04X index 11, Reserved = 0x%04X index 12, Reserved = 0x%04X index 13, Reserved = 0x%04X index 14, Reserved = 0x%04X index 15, Reserved = 0x%04X index 19, Reserved = 0x%04X index 20, TSTCNTL = 0x%04X index 21, TSTREAD1 = 0x%04X index 22, TSTREAD2 = 0x%04X index 23, TSTWRITE = 0x%04X index 24, Reserved = 0x%04X index 25, Reserved = 0x%04X index 26, Reserved = 0x%04X %s (disabled) PCI config ---------- %02x Bus Management Unit-------------------Blink SourceReceive Queue 1Sync Transmit Queue 1Async Transmit Queue 1Receive RAMbuffer 1Sync Transmit RAMbuffer 1Async Transmit RAMbuffer 1Receive MAC FIFO 1Transmit MAC FIFO 1Receive Queue 2Async Transmit Queue 2Sync Transmit Queue 2Receive RAMbuffer 2Sync Transmit RAMbuffer 2Async Transmit RAMbuffer 21Receive MAC FIFO 2Transmit MAC FIFO 2Descriptor PollEnd AddressReceive 1Transmit 1Receive 2Transmit 2 Status FIFOStatus levelTX statusISRRx GMAC 1%-32s 0x%08X Tx GMAC 1Rx GMAC 2Tx GMAC 2503_ISL3861503_ISL3863 503 503_ACC 505 505_2958 505A 505AMXAlmost Full ThreshControl/TestFIFO Flush MaskFIFO Flush ThresholdTruncation ThresholdUpper Pause ThresholdLower Pause ThresholdVLAN TagFIFO Write PointerFIFO Write LevelFIFO Read PointerFIFO Read Level81398139-K8139A8139A-G8139B81308139C81008100B/8139D8139C+81018169s8110s8169sb/8110sb8169sc/8110sc8102e8101e8168b/8111b8100e8168cp/8111cp8168c/8111c8168d/8111d8168dp/8111dp8105e8168e/8111e8168evl/8111evl8168f/8111f840284118106e8168g/8111gCFG = 0x%08x ESR = 0x%08x IER = 0x%08x TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x This driver version doesn't support information output for EMAC area, please update it or use older ethtool versionMR0 = 0x%08x MR1 = 0x%08x RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x TRTR = 0x%08x RWMR = 0x%08x IAR = %04x%08x LSA = %04x%08x VTPID = 0x%04x VTCI = 0x%04x IPGVR = 0x%04x STACR = 0x%08x OCTX = 0x%08x OCRX = 0x%08x MAHR = 0x%08x MALR = 0x%08x MMAHR = 0x%08x MMALR = 0x%08x REVID = 0x%08x IAHT = 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x GAHT = 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x FER = %08x SSR = %08x SMIISR = %08x REVID = %08x MR = %08x TSR = %08x SSR0 = %08x SSR1 = %08x SSR2 = %08x SSR3 = %08x SSR4 = %08x SSR5 = %08x CSR0: Status and Control 0x%04x CSR3: Interrupt Mask 0x%04x CSR4: Test and Features 0x%04x CSR5: Ext Control and Int 1 0x%04x CSR7: Ext Control and Int 2 0x%04x CSR15: Mode 0x%04x CSR40: Current RX Byte Count 0x%04x CSR41: Current RX Status 0x%04x CSR42: Current TX Byte Count 0x%04x CSR43: Current TX Status 0x%04x CSR88: Chip ID Lower 0x%04x CSR89: Chip ID Upper 0x%04x CSR112: Missed Frame Count 0x%04x CSR114: RX Collision Count 0x%04x BCR2: Misc. Configuration 0x%04x BCR9: Full-Duplex Control 0x%04x BCR18: Burst and Bus Control 0x%04x BCR19: EEPROM Control and Status 0x%04x BCR23: PCI Subsystem Vendor ID 0x%04x BCR24: PCI Subsystem ID 0x%04x BCR31: Software Timer 0x%04x BCR32: MII Control and Status 0x%04x BCR35: PCI Vendor ID 0x%04x End Address 0x%08X Write Pointer 0x%08X Read Pointer 0x%08X Packet Counter 0x%08X Level 0x%08X Control 0x%08X Control/Test 0x%08X Test 0x%02X Control 0x%02X Ram Buffer 0x%02X Connector type 0x%02X (%c) PMD type 0x%02X (%c) PHY type 0x%02X Chip Id 0x%02X Status 0x%04X Control 0x%04X Transmit 0x%04X Receive 0x%04X Transmit flow control 0x%04X Transmit parameter 0x%04X Serial mode 0x%04X Register Access Port 0x%02X LED Control/Status 0x%08X Interrupt Source 0x%08X Interrupt Mask 0x%08X Interrupt Hardware Error Source 0x%08X Interrupt Hardware Error Mask 0x%08X Interrupt Control 0x%08X Interrupt Moderation Mask 0x%08X Hardware Moderation Mask 0x%08X General Purpose I/O 0x%08X Buffer control 0x%04X Byte Counter %d Descriptor Address 0x%08X%08X Status 0x%08X Timestamp 0x%08X BMU Control/Status 0x%08X Done 0x%04X Request 0x%08X%08X Csum1 Offset %4d Position %d Csum2 Offset %4d Position %d Csum Start 0x%04X Pos %4d Write %d Start Address 0x%08x%08x ethtool_regs %-20s = %04x %-20s = %04x 0x00000: CTRL0 (Device control register) 0x%08X Link reset: %s VLAN mode: %s 0x00010: STATUS (Device status register) 0x%08X Link up: %s Bus type: %s Bus speed: %s Bus width: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Cononical form indicator: %s 0x00120: RDLEN (Receive desc length) 0x%08X 0x00128: RDH (Receive desc head) 0x%08X 0x00130: RDT (Receive desc tail) 0x%08X 0x00138: RDTR (Receive delay timer) 0x%08X 0x00600: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s 0x00610: TDLEN (Transmit desc length) 0x%08X 0x00618: TDH (Transmit desc head) 0x%08X 0x00620: TDT (Transmit desc tail) 0x%08X 0x00628: TIDV (Transmit delay timer) 0x%08X 0x042A4: LINKS (Link Status register) 0x%08X Link Status: %s Link Speed: %s 0x05080: FCTRL (Filter Control register) 0x%08X Broadcast Accept: %s Unicast Promiscuous: %s Multicast Promiscuous: %s Store Bad Packets: %s Receive Flow Control Packets: %s Receive Priority Flow Control Packets: %s Discard Pause Frames: %s Pass MAC Control Frames: %s 0x04294: MFLCN (TabMAC Flow Control register) 0x%08X Receive Flow Control Packets: %s Discard Pause Frames: %s Pass MAC Control Frames: %s Receive Priority Flow Control Packets: %s 0x03D00: RMCS (Receive Music Control register) 0x%08X Transmit Flow Control: %s Priority Flow Control: %s 0x03D00: FCCFG (Flow Control Configuration) 0x%08X Transmit Flow Control: %s Priority Flow Control: %s 0x04240: HLREG0 (Highlander Control 0 register) 0x%08X Transmit CRC: %s Receive CRC Strip: %s Jumbo Frames: %s Pad Short Frames: %s Loopback: %s 0x00000: CTRL (Device Control) 0x%08X 0x00008: STATUS (Device Status) 0x%08X 0x00018: CTRL_EXT (Extended Device Control) 0x%08X 0x00020: ESDP (Extended SDP Control) 0x%08X 0x00028: EODSDP (Extended OD SDP Control) 0x%08X 0x00200: LEDCTL (LED Control) 0x%08X 0x00048: FRTIMER (Free Running Timer) 0x%08X 0x0004C: TCPTIMER (TCP Timer) 0x%08X 0x%05X: FLA (Flash Access) 0x%08X 0x10110: EEMNGCTL (Manageability EEPROM Control) 0x%08X 0x10114: EEMNGDATA (Manageability EEPROM R/W Data) 0x%08X 0x10118: FLMNGCTL (Manageability Flash Control) 0x%08X 0x1011C: FLMNGDATA (Manageability Flash Read Data) 0x%08X 0x10120: FLMNGCNT (Manageability Flash Read Count) 0x%08X 0x1013C: FLOP (Flash Opcode) 0x%08X 0x%05X: GRC (General Receive Control) 0x%08X 0x00800: EICR (Extended Interrupt Cause) 0x%08X 0x00808: EICS (Extended Interrupt Cause Set) 0x%08X 0x00880: EIMS (Extended Interr. Mask Set/Read) 0x%08X 0x00888: EIMC (Extended Interrupt Mask Clear) 0x%08X 0x00810: EIAC (Extended Interrupt Auto Clear) 0x%08X 0x00890: EIAM (Extended Interr. Auto Mask EN) 0x%08X 0x00820: EITR0 (Extended Interrupt Throttle 0) 0x%08X 0x00900: IVAR0 (Interrupt Vector Allocation 0) 0x%08X 0x00000: MSIXT (MSI-X Table) 0x%08X 0x02000: MSIXPBA (MSI-X Pending Bit Array) 0x%08X 0x11068: PBACL (MSI-X PBA Clear) 0x%08X 0x00898: GPIE (General Purpose Interrupt EN) 0x%08X 0x03008: PFCTOP (Priority Flow Ctrl Type Opcode) 0x%08X 0x%05X: FCCTV%d (Flow Ctrl Tx Timer Value %d) 0x%08X 0x%05X: FCRTL%d (Flow Ctrl Rx Threshold low %d) 0x%08X 0x%05X: FCRTH%d (Flow Ctrl Rx Threshold High %d) 0x%08X 0x032A0: FCRTV (Flow Control Refresh Threshold) 0x%08X 0x0CE00: TFCS (Transmit Flow Control Status) 0x%08X 0x%05X: RDBAL%02d (Rx Desc Base Addr Low %02d) 0x%08X 0x%05X: RDBAH%02d (Rx Desc Base Addr High %02d) 0x%08X 0x%05X: RDLEN%02d (Receive Descriptor Length %02d) 0x%08X 0x%05X: RDH%02d (Receive Descriptor Head %02d) 0x%08X 0x%05X: RDT%02d (Receive Descriptor Tail %02d) 0x%08X 0x%05X: RXDCTL%02d (Receive Descriptor Control %02d) 0x%08X 0x%05X: SRRCTL%02d (Split and Replic Rx Control %02d) 0x%08X 0x%05X: DCA_RXCTRL%02d (Rx DCA Control %02d) 0x%08X 0x02F00: RDRXCTL (Receive DMA Control) 0x%08X 0x%05X: RXPBSIZE%d (Receive Packet Buffer Size %d) 0x%08X 0x03000: RXCTRL (Receive Control) 0x%08X 0x03D04: DROPEN (Drop Enable Control) 0x%08X 0x05000: RXCSUM (Receive Checksum Control) 0x%08X 0x05008: RFCTL (Receive Filter Control) 0x%08X 0x%05X: RAL%02d (Receive Address Low%02d) 0x%08X 0x%05X: RAH%02d (Receive Address High %02d) 0x%08X 0x05480: PSRTYPE (Packet Split Receive Type) 0x%08X 0x05090: MCSTCTRL (Multicast Control) 0x%08X 0x05818: MRQC (Multiple Rx Queues Command) 0x%08X 0x0581C: VMD_CTL (VMDq Control) 0x%08X 0x%05X: IMIR%d (Immediate Interrupt Rx %d) 0x%08X 0x%05X: IMIREXT%d (Immed. Interr. Rx Extended %d) 0x%08X 0x05AC0: IMIRVP (Immed. Interr. Rx VLAN Prior.) 0x%08X 0x%05X: TDBAL%02d (Tx Desc Base Addr Low %02d) 0x%08X 0x%05X: TDBAH%02d (Tx Desc Base Addr High %02d) 0x%08X 0x%05X: TDLEN%02d (Tx Descriptor Length %02d) 0x%08X 0x%05X: TDH%02d (Transmit Descriptor Head %02d) 0x%08X 0x%05X: TDT%02d (Transmit Descriptor Tail %02d) 0x%08X 0x%05X: TXDCTL%02d (Tx Descriptor Control %02d) 0x%08X 0x%05X: TDWBAL%02d (Tx Desc Compl. WB Addr low %02d) 0x%08X 0x%05X: TDWBAH%02d (Tx Desc Compl. WB Addr High %02d) 0x%08X 0x07E00: DTXCTL (DMA Tx Control) 0x%08X 0x%05X: DCA_TXCTRL%02d (Tx DCA Control %02d) 0x%08X 0x0CB00: TIPG (Transmit IPG Control) 0x%08X 0x%05X: TXPBSIZE%d (Transmit Packet Buffer Size %d) 0x%08X 0x0CD10: MNGTXMAP (Manageability Tx TC Mapping) 0x%08X 0x05800: WUC (Wake up Control) 0x%08X 0x05808: WUFC (Wake Up Filter Control) 0x%08X 0x05810: WUS (Wake Up Status) 0x%08X 0x05838: IPAV (IP Address Valid) 0x%08X 0x05840: IP4AT (IPv4 Address Table) 0x%08X 0x05880: IP6AT (IPv6 Address Table) 0x%08X 0x05900: WUPL (Wake Up Packet Length) 0x%08X 0x05A00: WUPM (Wake Up Packet Memory) 0x%08X 0x09000: FHFT (Flexible Host Filter Table) 0x%08X 0x07F40: DPMCS (Desc. Plan Music Ctrl Status) 0x%08X 0x0CD00: PDPMCS (Pkt Data Plan Music ctrl Stat) 0x%08X 0x050A0: RUPPBMR (Rx User Prior to Pkt Buff Map) 0x%08X 0x%05X: RT2CR%d (Receive T2 Configure %d) 0x%08X 0x%05X: RT2SR%d (Receive T2 Status %d) 0x%08X 0x%05X: TDTQ2TCCR%d (Tx Desc TQ2 TC Config %d) 0x%08X 0x%05X: TDTQ2TCSR%d (Tx Desc TQ2 TC Status %d) 0x%08X 0x%05X: TDPT2TCCR%d (Tx Data Plane T2 TC Config %d) 0x%08X 0x%05X: TDPT2TCSR%d (Tx Data Plane T2 TC Status %d) 0x%08X 0x04900: RTTDCS (Tx Descr Plane Ctrl&Status) 0x%08X 0x0CD00: RTTPCS (Tx Pkt Plane Ctrl&Status) 0x%08X 0x02430: RTRPCS (Rx Packet Plane Ctrl&Status) 0x%08X 0x%05X: RTRPT4C%d (Rx Packet Plane T4 Config %d) 0x%08X 0x%05X: RTRPT4S%d (Rx Packet Plane T4 Status %d) 0x%08X 0x%05X: RTTDT2C%d (Tx Descr Plane T2 Config %d) 0x%08X 0x%05X: RTTDT2S%d (Tx Descr Plane T2 Status %d) 0x%08X 0x%05X: RTTPT2C%d (Tx Packet Plane T2 Config %d) 0x%08X 0x%05X: RTTPT2S%d (Tx Packet Plane T2 Status %d) 0x%08X 0x03020: RTRUP2TC (Rx User Prio to Traffic Classes)0x%08X 0x0C800: RTTUP2TC (Tx User Prio to Traffic Classes)0x%08X 0x%05X: TXLLQ%d (Strict Low Lat Tx Queues %d) 0x%08X 0x04980: RTTBCNRM (DCB TX Rate Sched MMW) 0x%08X 0x0498C: RTTBCNRD (DCB TX Rate-Scheduler Drift) 0x%08X 0x04980: RTTQCNRM (DCB TX QCN Rate Sched MMW) 0x%08X 0x0498C: RTTQCNRR (DCB TX QCN Rate Reset) 0x%08X 0x08B00: RTTQCNCR (DCB TX QCN Control) 0x%08X 0x04A90: RTTQCNTG (DCB TX QCN Tagging) 0x%08X 0x04000: crcerrs (CRC Error Count) 0x%08X 0x04004: illerrc (Illegal Byte Error Count) 0x%08X 0x04008: errbc (Error Byte Count) 0x%08X 0x04010: mspdc (MAC Short Packet Discard Count) 0x%08X 0x%05X: mpc%d (Missed Packets Count %d) 0x%08X 0x04034: mlfc (MAC Local Fault Count) 0x%08X 0x04038: mrfc (MAC Remote Fault Count) 0x%08X 0x04040: rlec (Receive Length Error Count) 0x%08X 0x03F60: lxontxc (Link XON Transmitted Count) 0x%08X 0x0CF60: lxonrxc (Link XON Received Count) 0x%08X 0x03F68: lxofftxc (Link XOFF Transmitted Count) 0x%08X 0x0CF68: lxoffrxc (Link XOFF Received Count) 0x%08X 0x%05X: pxontxc%d (Priority XON Tx Count %d) 0x%08X 0x%05X: pxonrxc%d (Priority XON Received Count %d) 0x%08X 0x%05X: pxofftxc%d (Priority XOFF Tx Count %d) 0x%08X 0x%05X: pxoffrxc%d (Priority XOFF Received Count %d) 0x%08X 0x0405C: prc64 (Packets Received (64B) Count) 0x%08X 0x04060: prc127 (Packets Rx (65-127B) Count) 0x%08X 0x04064: prc255 (Packets Rx (128-255B) Count) 0x%08X 0x04068: prc511 (Packets Rx (256-511B) Count) 0x%08X 0x0406C: prc1023 (Packets Rx (512-1023B) Count) 0x%08X 0x04070: prc1522 (Packets Rx (1024-Max) Count) 0x%08X 0x04074: gprc (Good Packets Received Count) 0x%08X 0x04078: bprc (Broadcast Packets Rx Count) 0x%08X 0x0407C: mprc (Multicast Packets Rx Count) 0x%08X 0x04080: gptc (Good Packets Transmitted Count) 0x%08X 0x04088: gorcl (Good Octets Rx Count Low) 0x%08X 0x0408C: gorch (Good Octets Rx Count High) 0x%08X 0x04090: gotcl (Good Octets Tx Count Low) 0x%08X 0x04094: gotch (Good Octets Tx Count High) 0x%08X 0x%05X: rnbc%d (Receive No Buffers Count %d) 0x%08X 0x040A4: ruc (Receive Undersize count) 0x%08X 0x040A8: rfc (Receive Fragment Count) 0x%08X 0x040AC: roc (Receive Oversize Count) 0x%08X 0x040B0: rjc (Receive Jabber Count) 0x%08X 0x040B4: mngprc (Management Packets Rx Count) 0x%08X 0x040B8: mngpdc (Management Pkts Dropped Count) 0x%08X 0x0CF90: mngptc (Management Packets Tx Count) 0x%08X 0x040C0: torl (Total Octets Rx Count Low) 0x%08X 0x040C4: torh (Total Octets Rx Count High) 0x%08X 0x040D0: tpr (Total Packets Received) 0x%08X 0x040D4: tpt (Total Packets Transmitted) 0x%08X 0x040D8: ptc64 (Packets Tx (64B) Count) 0x%08X 0x040DC: ptc127 (Packets Tx (65-127B) Count) 0x%08X 0x040E0: ptc255 (Packets Tx (128-255B) Count) 0x%08X 0x040E4: ptc511 (Packets Tx (256-511B) Count) 0x%08X 0x040E8: ptc1023 (Packets Tx (512-1023B) Count) 0x%08X 0x040EC: ptc1522 (Packets Tx (1024-Max) Count) 0x%08X 0x040F0: mptc (Multicast Packets Tx Count) 0x%08X 0x040F4: bptc (Broadcast Packets Tx Count) 0x%08X 0x04120: xec (XSUM Error Count) 0x%08X 0x%05X: qprc%02d (Queue Packets Rx Count %02d) 0x%08X 0x%05X: qptc%02d (Queue Packets Tx Count %02d) 0x%08X 0x%05X: qbrc%02d (Queue Bytes Rx Count %02d) 0x%08X 0x%05X: qbtc%02d (Queue Bytes Tx Count %02d) 0x%08X 0x04200: PCS1GCFIG (PCS_1G Gloabal Config 1) 0x%08X 0x04208: PCS1GLCTL (PCS_1G Link Control) 0x%08X 0x0420C: PCS1GLSTA (PCS_1G Link Status) 0x%08X 0x04210: PCS1GDBG0 (PCS_1G Debug 0) 0x%08X 0x04214: PCS1GDBG1 (PCS_1G Debug 1) 0x%08X 0x04218: PCS1GANA (PCS-1G Auto Neg. Adv.) 0x%08X 0x0421C: PCS1GANLP (PCS-1G AN LP Ability) 0x%08X 0x04220: PCS1GANNP (PCS_1G Auto Neg Next Page Tx) 0x%08X 0x04224: PCS1GANLPNP (PCS_1G Auto Neg LPs Next Page) 0x%08X 0x04244: HLREG1 (Highlander Status 1) 0x%08X 0x04248: PAP (Pause and Pace) 0x%08X 0x0424C: MACA (MDI Auto-Scan Command and Addr) 0x%08X 0x04250: APAE (Auto-Scan PHY Address Enable) 0x%08X 0x04254: ARD (Auto-Scan Read Data) 0x%08X 0x04258: AIS (Auto-Scan Interrupt Status) 0x%08X 0x0425C: MSCA (MDI Single Command and Addr) 0x%08X 0x04260: MSRWD (MDI Single Read and Write Data) 0x%08X 0x04264: MLADD (MAC Address Low) 0x%08X 0x04268: MHADD (MAC Addr High/Max Frame size) 0x%08X 0x0426C: TREG (Test Register) 0x%08X 0x04288: PCSS1 (XGXS Status 1) 0x%08X 0x0428C: PCSS2 (XGXS Status 2) 0x%08X 0x04290: XPCSS (10GBASE-X PCS Status) 0x%08X 0x04298: SERDESC (SERDES Interface Control) 0x%08X 0x0429C: MACS (FIFO Status/CNTL Report) 0x%08X 0x042A0: AUTOC (Auto Negotiation Control) 0x%08X 0x042A8: AUTOC2 (Auto Negotiation Control 2) 0x%08X 0x042AC: AUTOC3 (Auto Negotiation Control 3) 0x%08X 0x042B0: ANLP1 (Auto Neg Lnk Part. Ctrl Word 1) 0x%08X 0x042B4: ANLP2 (Auto Neg Lnk Part. Ctrl Word 2) 0x%08X 0x04800: ATLASCTL (Atlas Analog Configuration) 0x%08X 0x02C20: RDSTATCTL (Rx DMA Statistic Control) 0x%08X 0x%05X: RDSTAT%d (Rx DMA Statistics %d) 0x%08X 0x02F08: RDHMPN (Rx Desc Handler Mem Page num) 0x%08X 0x02F10: RIC_DW0 (Rx Desc Hand. Mem Read Data 0) 0x%08X 0x02F14: RIC_DW1 (Rx Desc Hand. Mem Read Data 1) 0x%08X 0x02F18: RIC_DW2 (Rx Desc Hand. Mem Read Data 2) 0x%08X 0x02F1C: RIC_DW3 (Rx Desc Hand. Mem Read Data 3) 0x%08X 0x02F20: RDPROBE (Rx Probe Mode Status) 0x%08X 0x07C20: TDSTATCTL (Tx DMA Statistic Control) 0x%08X 0x%05X: TDSTAT%d (Tx DMA Statistics %d) 0x%08X 0x07F08: TDHMPN (Tx Desc Handler Mem Page Num) 0x%08X 0x%05X: TIC_DW%d (Tx Desc Hand. Mem Read Data %d) 0x%08X 0x07F20: TDPROBE (Tx Probe Mode Status) 0x%08X 0x0C600: TXBUFCTRL (TX Buffer Access Control) 0x%08X 0x%05X: TXBUFDATA%d (TX Buffer DATA %d) 0x%08X 0x03600: RXBUFCTRL (RX Buffer Access Control) 0x%08X 0x%05X: RXBUFDATA%d (RX Buffer DATA %d) 0x%08X 0x%05X: PCIE_DIAG%d (PCIe Diagnostic %d) 0x%08X 0x050A4: RFVAL (Receive Filter Validation) 0x%08X 0x042B8: MDFTC1 (MAC DFT Control 1) 0x%08X 0x042C0: MDFTC2 (MAC DFT Control 2) 0x%08X 0x042C4: MDFTFIFO1 (MAC DFT FIFO 1) 0x%08X 0x042C8: MDFTFIFO2 (MAC DFT FIFO 2) 0x%08X 0x042CC: MDFTS (MAC DFT Status) 0x%08X 0x1106C: PCIEECCCTL (PCIe ECC Control) 0x%08X 0x0C300: PBTXECC (Packet Buffer Tx ECC) 0x%08X 0x03300: PBRXECC (Packet Buffer Rx ECC) 0x%08X 0x08800: SECTXCTRL (Security Tx Control) 0x%08X 0x08804: SECTXSTAT (Security Tx Status) 0x%08X 0x08808: SECTXBUFFAF (Security Tx Buffer Almost Full) 0x%08X 0x08800: SECTXMINIFG (Security Tx Buffer Minimum IFG) 0x%08X 0x08800: SECRXCTRL (Security Rx Control) 0x%08X 0x08800: SECRXSTAT (Security Rx Status) 0x%08X 0x%05X: EEC (EEPROM/Flash Control) 0x%08X 0x10014: EERD (EEPROM Read) 0x%08X 0x05088: VLNCTRL (VLAN Control register) 0x%08X VLAN Mode: %s VLAN Filter: %s 0x02100: SRRCTL0 (Split and Replic Rx Control 0) 0x%08X Receive Buffer Size: %uKB 0x00: CR (Command): 0x%08x Transmit %s Receive %s 0x04: CFG (Configuration): 0x%08x %s Endian Boot ROM %s Internal Phy %s Phy Reset %s External Phy %s Default Auto-Negotiation %s, %s %s Mb %s Duplex Phy Interrupt %sAuto-Cleared Phy Configuration = 0x%02x Auto-Negotiation %s %s Polarity %s Duplex %d Mb/s Link %s 0x08: MEAR (EEPROM Access): 0x%08x 0x0c: PTSCR (PCI Test Control): 0x%08x EEPROM Self Test %s Rx Filter Self Test %s Tx FIFO Self Test %s Rx FIFO Self Test %s EEPROM Reload In Progress 0x10: ISR (Interrupt Status): 0x%08x 0x14: IMR (Interrupt Mask): 0x%08x 0x18: IER (Interrupt Enable): 0x%08x 0x20: TXDP (Tx Descriptor Pointer): 0x%08x 0x24: TXCFG (Tx Config): 0x%08x Drain Threshold = %d bytes (%d) Fill Threshold = %d bytes (%d) Max DMA Burst per Tx = %d bytes Automatic Tx Padding %s Mac Loopback %s Heartbeat Ignore %s Carrier Sense Ignore %s 0x30: RXDP (Rx Descriptor Pointer): 0x%08x 0x34: RXCFG (Rx Config): 0x%08x Drain Threshold = %d bytes (%d) Max DMA Burst per Rx = %d bytes Long Packets %s Tx Packets %s Runt Packets %s Error Packets %s 0x3c: CCSR (CLKRUN Control/Status): 0x%08x CLKRUNN %s Power Management %s Power Management Event Pending 0x40: WCSR (Wake-on-LAN Control/Status): 0x%08x Wake on Phy Interrupt Enabled Wake on Unicast Packet Enabled Wake on Multicast Packet Enabled Wake on Broadcast Packet Enabled Wake on Pattern 0 Match Enabled Wake on Pattern 1 Match Enabled Wake on Pattern 2 Match Enabled Wake on Pattern 3 Match Enabled Wake on Magic Packet Enabled Magic Packet SecureOn Enabled Unicast Packet Received Multicast Packet Received Broadcast Packet Received 0x44: PCR (Pause Control/Status): 0x%08x Pause Counter = %d Pause %sNegotiated Pause on DA %s Pause on Mulitcast %s Pause %s PS_RCVD: Pause Frame Received 0x48: RFCR (Rx Filter Control): 0x%08x Unicast Hash %s Multicast Hash %s Arp %s Pattern 0 Match %s Pattern 1 Match %s Pattern 2 Match %s Pattern 3 Match %s Perfect Match %s All Unicast %s All Multicast %s All Broadcast %s Rx Filter %s 0x4c: RFDR (Rx Filter Data): 0x%08x PMATCH 1-0 = 0x%08x PMATCH 3-2 = 0x%08x PMATCH 5-4 = 0x%08x PCOUNT 1-0 = 0x%08x PCOUNT 3-2 = 0x%08x SOPASS 1-0 = 0x%08x SOPASS 3-2 = 0x%08x SOPASS 5-4 = 0x%08x 0x50: BRAR (Boot ROM Address): 0x%08x Automatically Increment Address 0x54: BRDR (Boot ROM Data): 0x%08x 0x58: SRR (Silicon Revision): 0x%08x 0x5c: MIBC (Mgmt Info Base Control): 0x%08x Counter Overflow Warning 0x60: MIB[0] (Rx Errored Packets): 0x%04x 0x64: MIB[1] (Rx Frame Sequence Errors): 0x%02x 0x68: MIB[2] (Rx Missed Packets): 0x%02x 0x6c: MIB[3] (Rx Alignment Errors): 0x%02x 0x70: MIB[4] (Rx Symbol Errors): 0x%02x 0x74: MIB[5] (Rx Long Frame Errors): 0x%02x 0x78: MIB[6] (Tx Heartbeat Errors): 0x%02x 0x80: BMCR (Basic Mode Control): 0x%04x %s Duplex Port is Powered %s Auto-Negotiation %s %d Mb/s Auto-Negotiation Restarting 0x84: BMSR (Basic Mode Status): 0x%04x Link %s %sCapable of Auto-Negotiation Auto-Negotiation %sComplete %sCapable of Preamble Suppression %sCapable of 10Base-T Half Duplex %sCapable of 10Base-T Full Duplex %sCapable of 100Base-TX Half Duplex %sCapable of 100Base-TX Full Duplex %sCapable of 100Base-T4 Jabber Condition Detected 0x88: PHYIDR1 (PHY ID #1): 0x%04x 0x8c: PHYIDR2 (PHY ID #2): 0x%04x OUI = 0x%06x Model = 0x%02x (%d) Revision = 0x%01x (%d) 0x90: ANAR (Autoneg Advertising): 0x%04x Protocol Selector = 0x%02x (%d) Advertising 10Base-T Half Duplex Advertising 10Base-T Full Duplex Advertising 100Base-TX Half Duplex Advertising 100Base-TX Full Duplex Indicating Remote Fault 0x94: ANLPAR (Autoneg Partner): 0x%04x Supports 10Base-T Half Duplex Supports 10Base-T Full Duplex Supports 100Base-TX Half Duplex Supports 100Base-TX Full Duplex Indicates Acknowledgement 0x98: ANER (Autoneg Expansion): 0x%04x Link Partner Can %sAuto-Negotiate Link Code Word %sReceived Next Page %sSupported Link Partner Next Page %sSupported Parallel Detection Fault 0x9c: ANNPTR (Autoneg Next Page Tx): 0x%04x 0xc0: PHYSTS (Phy Status): 0x%04x Link %s %d Mb/s %s Duplex Auto-Negotiation %sComplete %s Polarity 0xc4: MICR (MII Interrupt Control): 0x%04x 0xc8: MISR (MII Interrupt Status): 0x%04x Rx Error Counter Half-Full Interrupt %s False Carrier Counter Half-Full Interrupt %s Auto-Negotiation Complete Interrupt %s Remote Fault Interrupt %s Jabber Interrupt %s Link Change Interrupt %s 0xcc: PGSEL (Phy Register Page Select): 0x%04x 0xd0: FCSCR (False Carrier Counter): 0x%04x 0xd4: RECR (Rx Error Counter): 0x%04x 0xd8: PCSR (100Mb/s PCS Config/Status): 0x%04x NRZI Bypass %s %s Signal Detect Algorithm %s Signal Detect Operation True Quiet Mode %s Rx Clock is %s 4B/5B Operation %s Forced 100 Mb/s Good Link 0xe4: PHYCR (Phy Control): 0x%04x Phy Address = 0x%x (%d) %sPause Compatible with Link Partner LED Stretching %s Phy Self Test %s Self Test Sequence = PSR%d 0xe8: TBTSCR (10Base-T Status/Control): 0x%04x Jabber %s Heartbeat %s Polarity Auto-Sense/Correct %s %s Polarity %s Normal Link Pulse %s 10 Mb/s Loopback %s Forced 10 Mb/s Good Link 0xe4: PMDCSR: 0x%04x 0xf4: DSPCFG: 0x%04x 0xf8: SDCFG: 0x%04x 0xfc: TSTDAT: 0x%04x RealTek RTL%s registers: -------------------------------------------------------- 0x00: MAC Address %02x:%02x:%02x:%02x:%02x:%02x 0x08: Multicast Address Filter 0x%08x 0x%08x Unknown RealTek chip (TxConfig: 0x%08x) 0x10: Dump Tally Counter Command 0x%08x 0x%08x 0x20: Tx Normal Priority Ring Addr 0x%08x 0x%08x 0x28: Tx High Priority Ring Addr 0x%08x 0x%08x 0x10: Transmit Status Desc 0 0x%08x 0x14: Transmit Status Desc 1 0x%08x 0x18: Transmit Status Desc 2 0x%08x 0x1C: Transmit Status Desc 3 0x%08x 0x20: Transmit Start Addr 0 0x%08x 0x24: Transmit Start Addr 1 0x%08x 0x28: Transmit Start Addr 2 0x%08x 0x2C: Transmit Start Addr 3 0x%08x 0x30: Flash memory read/write 0x%08x 0x30: Rx buffer addr (C mode) 0x%08x 0x34: Early Rx Byte Count %8u 0x36: Early Rx Status 0x%02x 0x37: Command 0x%02x Rx %s, Tx %s%s 0x38: Current Address of Packet Read (C mode) 0x%04x 0x3A: Current Rx buffer address (C mode) 0x%04x 0x3C: Interrupt Mask 0x%04x 0x3E: Interrupt Status 0x%04x 0x40: Tx Configuration 0x%08x 0x44: Rx Configuration 0x%08x 0x48: Timer count 0x%08x 0x4C: Missed packet counter 0x%06x 0x50: EEPROM Command 0x%02x 0x51: Config 0 0x%02x 0x52: Config 1 0x%02x 0x53: Config 2 0x%02x 0x54: Config 3 0x%02x 0x55: Config 4 0x%02x 0x56: Config 5 0x%02x 0x58: Timer interrupt 0x%08x 0x5C: Multiple Interrupt Select 0x%04x 0x60: PHY access 0x%08x 0x54: Timer interrupt 0x%08x 0x58: Media status 0x%02x 0x59: Config 3 0x%02x 0x5A: Config 4 0x%02x 0x64: TBI control and status 0x%08x 0x68: TBI Autonegotiation advertisement (ANAR) 0x%04x 0x6A: TBI Link partner ability (LPAR) 0x%04x 0x6C: PHY status 0x%02x 0x84: PM wakeup frame 0 0x%08x 0x%08x 0x8C: PM wakeup frame 1 0x%08x 0x%08x 0x94: PM wakeup frame 2 (low) 0x%08x 0x%08x 0x9C: PM wakeup frame 2 (high) 0x%08x 0x%08x 0xA4: PM wakeup frame 3 (low) 0x%08x 0x%08x 0xAC: PM wakeup frame 3 (high) 0x%08x 0x%08x 0xB4: PM wakeup frame 4 (low) 0x%08x 0x%08x 0xBC: PM wakeup frame 4 (high) 0x%08x 0x%08x 0xC4: Wakeup frame 0 CRC 0x%04x 0xC6: Wakeup frame 1 CRC 0x%04x 0xC8: Wakeup frame 2 CRC 0x%04x 0xCA: Wakeup frame 3 CRC 0x%04x 0xCC: Wakeup frame 4 CRC 0x%04x 0xDA: RX packet maximum size 0x%04x 0x78: PHY parameter 1 0x%08x 0x7C: Twister parameter 0x%08x 0x80: PHY parameter 2 0x%02x 0x82: Low addr of a Tx Desc w/ Tx DMA OK 0x%04x 0x82: MII register 0x%02x 0x84: PM CRC for wakeup frame 0 0x%02x 0x85: PM CRC for wakeup frame 1 0x%02x 0x86: PM CRC for wakeup frame 2 0x%02x 0x87: PM CRC for wakeup frame 3 0x%02x 0x88: PM CRC for wakeup frame 4 0x%02x 0x89: PM CRC for wakeup frame 5 0x%02x 0x8A: PM CRC for wakeup frame 6 0x%02x 0x8B: PM CRC for wakeup frame 7 0x%02x 0x8C: PM wakeup frame 0 0x%08x 0x%08x 0x94: PM wakeup frame 1 0x%08x 0x%08x 0x9C: PM wakeup frame 2 0x%08x 0x%08x 0xA4: PM wakeup frame 3 0x%08x 0x%08x 0xAC: PM wakeup frame 4 0x%08x 0x%08x 0xB4: PM wakeup frame 5 0x%08x 0x%08x 0xBC: PM wakeup frame 6 0x%08x 0x%08x 0xC4: PM wakeup frame 7 0x%08x 0x%08x 0xCC: PM LSB CRC for wakeup frame 0 0x%02x 0xCD: PM LSB CRC for wakeup frame 1 0x%02x 0xCE: PM LSB CRC for wakeup frame 2 0x%02x 0xCF: PM LSB CRC for wakeup frame 3 0x%02x 0xD0: PM LSB CRC for wakeup frame 4 0x%02x 0xD1: PM LSB CRC for wakeup frame 5 0x%02x 0xD2: PM LSB CRC for wakeup frame 6 0x%02x 0xD3: PM LSB CRC for wakeup frame 7 0x%02x 0xD4: Flash memory read/write 0x%08x 0xD8: Config 5 0x%02x 0xE0: C+ Command 0x%04x 0xE2: Interrupt Mitigation 0x%04x TxTimer: %u TxPackets: %u RxTimer: %u RxPackets: %u 0xE4: Rx Ring Addr 0x%08x 0x%08x 0xEC: Early Tx threshold 0x%02x 0xFC: External MII register 0x%08x 0xF0: Func Event 0x%08x 0xF4: Func Event Mask 0x%08x 0xF8: Func Preset State 0x%08x 0xFC: Func Force Event 0x%08x 0x5E: PCI revision id 0x%02x 0x60: Transmit Status of All Desc (C mode) 0x%04x 0x62: MII Basic Mode Control Register 0x%04x 0x64: MII Basic Mode Status Register 0x%04x 0x66: MII Autonegotiation Advertising 0x%04x 0x68: MII Link Partner Ability 0x%04x 0x6A: MII Expansion 0x%04x 0x6C: MII Disconnect counter 0x%04x 0x6E: MII False carrier sense counter 0x%04x 0x70: MII Nway test 0x%04x 0x72: MII RX_ER counter 0x%04x 0x74: MII CS configuration 0x%04x offset 0x50, ID_REV = 0x%08X offset 0x54, INT_CFG = 0x%08X offset 0x58, INT_STS = 0x%08X offset 0x5C, INT_EN = 0x%08X offset 0x60, RESERVED = 0x%08X offset 0x64, BYTE_TEST = 0x%08X offset 0x68, FIFO_INT = 0x%08X offset 0x6C, RX_CFG = 0x%08X offset 0x70, TX_CFG = 0x%08X offset 0x74, HW_CFG = 0x%08X offset 0x78, RX_DP_CTRL = 0x%08X offset 0x7C, RX_FIFO_INF = 0x%08X offset 0x80, TX_FIFO_INF = 0x%08X offset 0x84, PMT_CTRL = 0x%08X offset 0x88, GPIO_CFG = 0x%08X offset 0x8C, GPT_CFG = 0x%08X offset 0x90, GPT_CNT = 0x%08X offset 0x94, FPGA_REV = 0x%08X offset 0x98, ENDIAN = 0x%08X offset 0x9C, FREE_RUN = 0x%08X offset 0xA0, RX_DROP = 0x%08X offset 0xA4, MAC_CSR_CMD = 0x%08X offset 0xA8, MAC_CSR_DATA = 0x%08X offset 0xAC, AFC_CFG = 0x%08X offset 0xB0, E2P_CMD = 0x%08X offset 0xB4, E2P_DATA = 0x%08X index 0, Basic Control Reg = 0x%04X index 1, Basic Status Reg = 0x%04X index 2, PHY identifier 1 = 0x%04X index 3, PHY identifier 2 = 0x%04X index 4, Auto Negotiation Advertisement Reg = 0x%04X index 5, Auto Negotiation Link Partner Ability Reg = 0x%04X index 6, Auto Negotiation Expansion Register = 0x%04X index 16, Silicon Revision Reg = 0x%04X index 17, Mode Control/Status Reg = 0x%04X index 18, Special Modes = 0x%04X index 27, Control/Status Indication = 0x%04X index 28, Special internal testability = 0x%04X index 29, Interrupt Source Register = 0x%04X index 30, Interrupt Mask Register = 0x%04X index 31, PHY Special Control/Status Register = 0x%04X Hardware Version %s Start Address 0x%08X Upper Threshold/Pause Packets 0x%08X Lower Threshold/Pause Packets 0x%08X Upper Threshold/High Priority 0x%08X Lower Threshold/High Priority 0x%08X Descriptor Address 0x%08X%08X Address Counter 0x%08X%08X Current Byte Counter %d Flag & FIFO Address 0x%08X Next 0x%08X Data 0x%08X%08X CSR Receive Queue 1 0x%08X CSR Sync Queue 1 0x%08X CSR Async Queue 1 0x%08X CSR Receive Queue 2 0x%08X CSR Async Queue 2 0x%08X CSR Sync Queue 2 0x%08X Write Pointer 0x%02X Read Pointer 0x%02X Level 0x%02X Watermark 0x%02X ISR Watermark 0x%02X GMAC control 0x%04X GPHY control 0x%04X LINK control 0x%02hX #$$-$E$]$u$!(( )$)D)d)))))*$*(D]D]D]D]D]C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C39]9]9]C39]9]C3C3C3C3C3C39]C3C3]discardedaccepted2048 bytes1024 bytes512 bytes256 bytesbits [47:36]bits [43:32]bits [39:28]bits [35:24]multicast onlyunicast onlymulticast and unicastsourcedestination%04d: 0x%08X Super MULTI: %02x:%02x:%02x:%02x:%02x:%02x Ports: 0x%x VLAN: %04d Secure Block DLR UNI : ALE Entries (%d): %04d: %s OUI : VLAN %04d: member: 0x%x mc flood unreg: 0x%x mc flood reg: 0x%x untag: 0x%x %s = %s: %4zu Row %-*s %*s%4zuST MAC 10/100 Registers control reg 0x%08X addr HI 0x%08X addr LO 0x%08X multicast hash HI 0x%08X multicast hash LO 0x%08X MII addr 0x%08X MII data %08X flow control 0x%08X VLAN1 tag 0x%08X VLAN2 tag 0x%08X mac wakeup frame 0x%08X mac wakeup crtl 0x%08X CSR%d 0x%08X DMA cur tx buf addr 0x%08X DMA cur rx buf addr 0x%08X ST GMAC Registers Reg%d 0x%08X Core Version %d.%d (0)TX_EN %d (1)RX_EN %d (2)XON_GEN %d (3)ETH_SPEED %d (4)PROMIS_EN %d (5)PAD_EN %d (6)CRC_FWD %d (7)PAUSE_FWD %d (8)PAUSE_IGN %d (9)TXADDR_INS %d (10)HD_EN %d (11)EXCESS_COL %d (12)LATE_COL %d (13)SW_RESET %d (14)MHASH_SEL %d (15)LOOP_EN %d (16-18)TX_ADDR_SEL %d (19)MAGIC_EN %d (20)SLEEP %d (21)WAKEUP %d (22)XOFF_GEN %d (23)CTRL_FRAME_EN %d (24)NO_LEN_CHECK %d (25)ENA_10 %d (26)RX_ERR_DISC %d (31)CTRL_RESET %d Control Registers Datapath Registers ================== Transmit Queue %d ---------------- Transmit Ring Transmit Data Ring Receive Queue %d Receive Ring 0 Receive Ring 1 Receive Data Ring LAN78xx Registers: ID_REV = 0x%08X INT_STS = 0x%08X HW_CFG = 0x%08X PMT_CTRL = 0x%08X E2P_CMD = 0x%08X E2P_DATA = 0x%08X USB_STATUS = 0x%08X VLAN_TYPE = 0x%08X MAC Registers: MAC_CR = 0x%08X MAC_RX = 0x%08X MAC_TX = 0x%08X FLOW = 0x%08X ERR_STS = 0x%08X MII_ACC = 0x%08X MII_DATA = 0x%08X EEE_TX_LPI_REQ_DLY = 0x%08X EEE_TW_TX_SYS = 0x%08X EEE_TX_LPI_REM_DLY = 0x%08X WUCSR = 0x%08X PHY Registers: Mode Control = 0x%04X Mode Status = 0x%04X 1000BASE-T Control = 0x%04X 1000BASE-T Status = 0x%04X Reserved = 0x%04X Bypass Control = 0x%04X Interrupt Mask = 0x%04X Interrupt Status = 0x%04X LED Mode Select = 0x%04X LED Behavior = 0x%04X PL Signal integrity errorsPXP Registers ------ ------- PCIe statistics: %-30s : LAN743x Registers: CHIP_ID_REV = 0x%08X FPGA_REV = 0x%08X STRAP_READ = 0x%08X MAC_CR = 0x%08X MAC_RX = 0x%08X MAC_TX = 0x%08X FLOW = 0x%08X MII_ACC = 0x%08X MII_DATA = 0x%08X WUCSR = 0x%08X WK_SRC = 0x%08X %-*s : 0x%016llx module_temperature%gModule temperaturemodule_voltageModule voltage %-41s : %.4f V vendor_ouiVendor OUI %-41s : %s %s_%u%s_description %-41s : 0x%02xEncodingconnectorConnectorCopper cable,%s unequalized%s passive equalized%s linear active equalizerstransmitter_technologyTransmitter technology %-41s : %u%s %-41s : %.04f%s %-41s : Receiver signal OMARcvr signal avg optical powerModule temperature high alarmOnLaser bias current high alarmlaser_tx_bias_currentLaser tx bias current%s (Channel %d) %-41s : %.3f mA transmit_avg_optical_powerTransmit avg optical power %-41s : %.4f mW / %.2f dBm %s (Chan %d)majorminor %-41s : %d.%d GBIC compliant with MOD_DEF%s %uextended_identifierExtended identifiertransceiver_codesTransceiver codesTransceiver typeMBdBR Nominalrate_identifierRate identifierLength (SMF)Length (OM2)Length (OM1)Length (OM3) [SFF-8472 rev10.4 only]passive_cu_cmplnce.Passive Cu cmplnce.Active Cu cmplnce.active_cu_cmplnce.nmLaser wavelengthVendor nameVendor PNVendor revoption_valuesOption values %-41s : 0x%02x 0x%02x Option%BR margin maxBR margin minVendor SNDate codelaser_bias_currentLaser bias currentlaser_output_powerLaser output poweroptical_diagnostics_supportOptical diagnostics support %-41s : 0x%02x %s %s CDR present in RX No CDR in RXpower_setPower setpower_overridePower overridedbAttenuation at 2.5GHzAttenuation at 5.0GHzAttenuation at 7.0GHzAttenuation at 12.9GHzLaser wavelength toleranceRevision ComplianceRx loss of signalTx loss of signalRx loss of lockTx loss of lockTx faultTx adaptive eq faultNot supportedSingle writeMultiple writesPower classMax power> 6.3kmCable assembly lengthTx CDR bypass controlRx CDR bypass controlTx CDRRx CDRAttenuation at 5GHzAttenuation at 7GHzAttenuation at 25.8GHzLength (OM5)Length (OM4)CLEI coderevision_complianceRevision compliance %-41s : Rev. %d.%d module_stateModule statemodule_fault_causeModule Fault Causelow_pwr_allow_request_hwLowPwrAllowRequestHWlow_pwr_request_swLowPwrRequestSWActive firmware versionInactive firmware versionCDB instancesCDB background modeCDB EPL pagesCDB Maximum EPL RW lengthCDB Maximum LPL RW lengthCDB trigger methodRESERVED[0x%05x]: 0x%08x expected 0x%8X actual 0x%8X FBNIC_INTR_MASK%s[%d]: 0x%08x FBNIC_INTR_STATUSFBNIC_INTR_SW_STATUSFBNIC_INTR_SW_AC_MODEFBNIC_INTR_RCQ_TIMEOUTFBNIC_INTR_TCQ_TIMEOUTFBNIC_QM_TWQ_IDLEFBNIC_QM_TWQ_ERR_INTR_STSFBNIC_QM_TWQ_ERR_INTR_MASKFBNIC_QM_TQS_CTL0: 0x%08x [0:0] LSO_TS_CTL: 0x%08x FBNIC_QM_TQS_CTL1: 0x%08x [13:0] BMC_FW_MTU: 0x%08x FBNIC_QM_TCQ_CTL0: 0x%08x FBNIC_QM_TCQ_CTL1: 0x%08x [1:0] WR_AXI_ERRS: 0x%02x [3:0] TWD_ERRORS: 0x%02x [5:0] RANGE0: 0x%05x [13:8] RANGE1: 0x%05x [21:16] RANGE2: 0x%05x [29:24] RANGE3: 0x%05x FBNIC_QM_TNI_TDF_CTL: 0x%08x [1:0] MRRS: 0x%05x [3:2] CLS: 0x%05x [11:4] MAX_OT: 0x%05x [23:12] MAX_OB: 0x%05x FBNIC_QM_TNI_TDE_CTL: 0x%08x [24:12] MAX_OB: 0x%05x [25:25] MRRS1KB: 0x%05x FBNIC_QM_TNI_TCM_CTL: 0x%08x [1:0] MPS: 0x%05x FBNIC_QM_TNI_TCM_STS: 0x%02x [0] TDF_NOCIF_IDLE: 0x%02x [1] TDE_NOCIF_IDLE: 0x%02x [2] TCM_NOCIF_IDLE: 0x%02x FBNIC_QM_RCQ_IDLEFBNIC_QM_RCQ_ERR_INTR_STSFBNIC_QM_RCQ_ERROR_INTR_MASKFBNIC_QM_RCQ_CTL0: 0x%08x FBNIC_QM_RCQ_CTL1: 0x%08x FBNIC_QM_HPQ_IDLEFBNIC_QM_PPQ_IDLEFBNIC_QM_BDQ_ERROR_INTR_STSFBNIC_QM_BDQ_ERROR_INTR_MASKFBNIC_QM_BDQ_CTL0FBNIC_QM_RDE_STS [00:00] IDLE: 0x%08x FBNIC_QM_RDE_CTL: 0x%08x FBNIC_QM_RNI_RBP_CTL: 0x%08x [01:00] MRRS: 0x%05x [03:02] CLS: 0x%05x [11:04] MAX_OT: 0x%05x FBNIC_QM_RNI_RDE_CTL: 0x%08x [01:00] MPS: 0x%05x FBNIC_QM_RNI_RCM_CTL: 0x%08x FBNIC_QM_RNI_STS: 0x%08x [01:01] VALUE: 0x%02x FBNIC_TCE_LSO_CTRL: 0x%08x FBNIC_TCE_CSO_CTRL: 0x%08x FBNIC_TCE_TXB_CTRL: 0x%08x [00:00] LOAD: 0x%02x [02:02] TXB_DIS: 0x%02x [07:00] WEIGHT_0: 0x%05x [15:08] WEIGHT_1: 0x%05x [23:16] WEIGHT_2: 0x%05x [10:00] START: 0x%05x [22:11] SIZE: 0x%05x [07:00] QUANTUM_0: 0x%05x [15:08] QUANTUM_1: 0x%05x [23:16] QUANTUM_2: 0x%05x [05:00] NUM_SLOT: 0x%08x FBNIC_TCE_TXB_CLDR_SLOT_CFGFBNIC_TCE_TXB_FRMS_SRCFBNIC_TCE_TXB_FRMS_DESTFBNIC_TCE_TXB_BYTES_SRC_LFBNIC_TCE_TXB_BYTES_SRC_HFBNIC_TCE_TXB_BYTES_DEST_LFBNIC_TCE_TXB_BYTES_DEST_HFBNIC_TCE_INTR_STS: 0x%08x FBNIC_TCE_TXB_DATA_FIFO_LEVEL [12:00] FIFO_LEVEL: 0x%05x FBNIC_TCE_DROP_CTRL: 0x%08x [23:16] TBI_FIFO: 0x%05x [03:00] DEST_ID_0: 0x%02x [07:04] DEST_ID_1: 0x%02x [11:08] DEST_ID_2: 0x%02x [15:12] DEST_ID_3: 0x%02x [19:16] DEST_ID_4: 0x%02x [23:20] DEST_ID_5: 0x%02x [27:24] DEST_ID_6: 0x%02x [31:28] DEST_ID_7: 0x%02x [07:00] QUANTUM0: 0x%05x [15:08] QUANTUM1: 0x%05x [23:16] QUANTUM2: 0x%05x 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OUTGPIO14_OUTGPIO15_OUTGPIO8_OENGPIO9_OENGPIO10_OENGPIO11_OENGPIO12_OENGPIO13_OENGPIO14_OENGPIO15_OENGPIO_PWRUP_VALUE2GPIO_IN2GPIO_OUT2GPIO_PWRUP_VALUE3GPIO_IN3GPIO_OUT3STRAP_PINSATE_MODEEE_PRSTSF_PRSTONCHIP_SRAMREVISION_IDEE_STRAPEE_STRAP_ENAER_DISEE_VPD_ENEE_VPD_EN_AD9_MODEEE_VPD_DEV_SF_SELEE_VPD_ACCESS_BLOCKEE_VPD_ACCESS_ONEE_VPD_AD_SIZEEE_VPD_LENGTHEE_VPD_BASEEE_VPD_WR_CMD_ENEE_VPDW_BASEEE_VPDW_LENGTHEE_EE_WR_TMR_VALUEEE_EE_CLOCK_DIVEE_VPD_WIP_POLLEE_SF_CLOCK_DIVEE_SF_FASTRD_ENEE_EXP_ROM_WINDOW_BASEEE_EXPROM_MASKEE_SPI_HDATA0EE_SPI_HDATA1EE_SPI_HDATA2EE_SPI_HDATA3EE_SPI_HADR_ADREE_SPI_HADR_DUBYTEEE_SPI_HCMD_ENCEE_SPI_HCMD_ADBCNTEE_SPI_HCMD_DUBCNTEE_SPI_HCMD_READEE_SPI_HCMD_DABCNTEE_SPI_HCMD_SF_SELEE_WR_TIMER_ACTIVEEE_SPI_HCMD_CMD_ENDFLT_EVQUSREV_DISTLP_TDTD_SELATTR_SELTLP_EPUS_DISABLEWD_TIMERINTA_VECINTB_VECTLP_ATTRTLP_TCPOST_WR_MASKFC_BLOCKING_ENB2B_REQ_ENPE_EIDLE_DISTX_RREQ_MASK_ENDOORBELL_DROPTRGT_MASK_ALLTX_MRG_TAGSPCIE_CPL_TIMEOUT_CTRLBDMRD_CPLF_FULLINT_ADR_CHARNORM_INT_VEC_DIS_CHARINT_ADR_KERNORM_INT_VEC_DIS_KERDRV_INT_EN_CHARCHAR_INT_KERCHAR_INT_CHARCHAR_INT_LEVE_SELDRV_INT_EN_KERKER_INT_KERKER_INT_CHARKER_INT_LEVE_SELADR_REGION0ADR_REGION1ADR_REGION2ADR_REGION3cmdq_regsring_regstqp_intr_regsdfx_32_regsdfx_64_regsdfx_bios_common_regsdfx_ssu_0_regsdfx_ssu_1_regsdfx_igu_egu_regsdfx_rpu_0_regsdfx_rpu_1_regsdfx_ncsi_regsdfx_rtc_regsdfx_ppp_regsdfx_rcb_regsdfx_tqp_regsdfx_ssu_2_regsdfx_rpu_tnlfree entryVLAN entryVLAN address entryinvalidBlocking/Forwarding/Learning%lluDL Signal integrity errorsTLP Signal integrity errorsLink integrityTX TLP traffic rateRX TLP traffic rateTX DLLP traffic rateRX DLLP traffic rateEqualization Phase 0 time(ms)Equalization Phase 1 time(ms)Equalization Phase 2 time(ms)Equalization Phase 3 time(ms)PHY LTSSM Histogram 0PHY LTSSM Histogram 1PHY LTSSM Histogram 2PHY LTSSM Histogram 3Recovery Histogram 0Recovery Histogram 1Laser bias current low alarmLaser tx power high alarmLaser tx power low alarmLaser tx power high warningLaser tx power low warningLaser rx power high alarmLaser rx power low alarmLaser rx power high warningLaser rx power low warningModule temperature low alarmModule voltage high alarmModule voltage low alarmModule voltage high warningModule voltage low warningLaser output power high alarmLaser output power low alarmTX_IPFIL_TBLTX_SRC_MAC_TBLRX_DESC_PTR_TBL_KERRX_DESC_PTR_TBLTX_DESC_PTR_TBL_KERTX_DESC_PTR_TBLEVQ_PTR_TBL_KEREVQ_PTR_TBLBUF_FULL_TBL_KERBUF_FULL_TBLRX_MAC_FILTER_TBL0TIMER_TBLTX_PACE_TBLRX_INDIRECTION_TBLTX_MAC_FILTER_TBL0MC_TREG_SMEMRX_FILTER_TBL0BIU_MC_SFT_STATUSHW_INITUSR_EV_CFGEE_SPI_HCMDEE_SPI_HADREE_SPI_HDATAEE_BASE_PAGEEE_VPD_CFG0NIC_STATGPIO_CTLGLB_CTLDP_CTRLMEM_STATCS_DEBUGALTERA_BUILDCSR_SPAREPCIE_SD_CTL0123PCIE_SD_CTL45PCIE_PCS_CTL_STATEVQ_CTLEVQ_CNT1EVQ_CNT2BUF_TBL_CFGSRM_RX_DC_CFGSRM_TX_DC_CFGSRM_CFGSRM_UPD_EVQSRAM_PARITYRX_FILTER_CTLRX_DC_PF_WMRX_RSS_TKEYRX_SELF_RSTRX_RSS_IPV6_REG1RX_RSS_IPV6_REG2RX_RSS_IPV6_REG3TX_CHKSM_CFGTX_RESERVEDTX_VLANTX_IPFIL_PORTENMD_CSMD_IDMAC_STAT_DMAMAC_CTRLGEN_MODEMAC_MC_HASH_REG0MAC_MC_HASH_REG1GM_CFG1GM_CFG2GM_ADR1GM_ADR2GMF_CFG0GMF_CFG1GMF_CFG2GMF_CFG3GMF_CFG4GMF_CFG5TX_SRC_MAC_CTLXM_GLB_CFGXM_TX_CFGXM_RX_CFGXM_MGT_INT_MASKXM_FCXM_TX_PARAMXM_RX_PARAMXX_PWR_RSTXX_SD_CTLXX_TXDRV_CTLBIU_HW_REV_IDMC_DB_LWRDMC_DB_HWRD%04d: RCTL (Receive Control Register) Receiver: %s Stop Bad Packets: %s Unicast Promiscuous: %s Multicast Promiscuous: %s Long Packet Reception: %s Loopback Model: %s Hash Select for MTA: %s Multicast/Unicast Table Offset: %s Broadcast Accept Mode: %s Receive Buffer Size: %s VLAN Filter: %s Canonical Form Indicator: %s Canonical Form Indicator Bit: %s Pad Small Receive Packets: %s Discard Pause Frames: %s Pass MAC Control Frames: %s Strip Ethernet CRC: %s %04d: RAL (Receive Address Low %02d) Receive Address Low: %08X %04d: RAH (Receive Address High %02d) Receive Address High: %04X Address Select: %s Queue Select: %d Queue Select Enable: %s Address Valid: %s %04d: VLANPQF (VLAN Priority Queue Filter) Priority 0 Queue: %d Packet Buffer: %s Valid: %s Priority 1 Queue: %d Packet Buffer: %s Valid: %s Priority 2 Queue: %d Packet Buffer: %s Valid: %s Priority 3 Queue: %d Packet Buffer: %s Valid: %s Priority 4 Queue: %d Packet Buffer: %s Valid: %s Priority 5 Queue: %d Packet Buffer: %s Valid: %s Priority 6 Queue: %d Packet Buffer: %s Valid: %s Priority 7 Queue: %d Packet Buffer: %s Valid: %s %04d: ETQF (EType Queue Filter %d) EType: %04X EType Length: %d EType Length Enable: %s Queue: %d Queue Enable: %s Immediate Interrupt: %s 1588 Time Stamp: %s Filter Enable: %s 0x00000: VFCTRL (VF Control Register) (Write Only) N/A 0x00008: VFSTATUS (VF Status Register) 0x%08X 0x00010: VFLINKS (VF Link Status Register) 0x%08X 0x03190: VFRXMEMWRAP (Rx Packet Buffer Flush Detect) 0x%08X 0x00048: VFFRTIMER (VF Free Running Timer) 0x%08X 0x00100: VFEICR (VF Extended Interrupt Cause) 0x%08X 0x00104: VFEICS (VF Extended Interrupt Cause Set) 0x%08X 0x00108: VFEIMS (VF Extended Interrupt Mask Set) 0x%08X 0x0010C: VFEIMC (VF Extended Interrupt Mask Clear) 0x%08X 0x00110: VFEIAC (VF Extended Interrupt Auto Clear) 0x%08X 0x00114: VFEIAM (VF Extended Interrupt Auto Mask) 0x%08X 0x00820: VFEITR(0) (VF Extended Interrupt Throttle) 0x%08X 0x00120: VFIVAR(0) (VF Interrupt Vector Allocation) 0x%08X 0x00140: VFIVAR_MISC (VF Interrupt Vector Misc) 0x%08X 0x00104: VFPSRTYPE (VF Replication Packet Split Type) 0x%08X 0x%05x: VFRDBAL(%d) (VF Rx Desc. Base Addr Low %d) 0x%08X 0x%05x: VFRDBAH(%d) (VF Rx Desc. Base Addr High %d) 0x%08X 0x%05x: VFRDLEN(%d) (VF Rx Desc. Length %d) 0x%08X 0x%05x: VFRDH(%d) (VF Rx Desc. Head %d) 0x%08X 0x%05x: VFRDT(%d) (VF Rx Desc. Tail %d) 0x%08X 0x%05x: VFRDT(%d) (VF Rx Desc. Control %d), 0x%08X 0x%05x: VFSRRCTL(%d) (VF Split Rx Control %d) 0x%08X 0x%05x: VFTDBAL(%d) (VF Tx Desc. Base Addr Low %d) 0x%08X 0x%05x: VFTDBAH(%d) (VF Tx Desc. Base Addr High %d) 0x%08X 0x%05x: VFTDLEN(%d) (VF Tx Desc. Length %d) 0x%08X 0x%05x: VFTDH(%d) (VF Tx Desc. Head %d) 0x%08X 0x%05x: VFTDT(%d) (VF Tx Desc. Tail %d) 0x%08X 0x%05x: VFTDT(%d) (VF Tx Desc. Control %d) 0x%08X 0x%05x: VFTDWBAL(%d) (VF Tx Desc. Write Back Addr Lo %d) 0x%08X 0x%05x: VFTDWBAH(%d) (VF Tx Desc. Write Back Addr Hi %d) 0x%08X Altera TSE 10/100/1000 Registers, Version %d --------------------------------------------- Revision 0x%08X CustVersion 0x%08X Scratch 0x%08X Command/Config 0x%08X mac_0 0x%08X mac_1 0x%08X frm_length 0x%08X pause_quant 0x%08X rx_section_empty 0x%08X rx_section_full 0x%08X tx_section_empty 0x%08X tx_section_full 0x%08X rx_almost_empty 0x%08X rx_almost_full 0x%08X tx_almost_empty 0x%08X tx_almost_full 0x%08X mdio_addr0 0x%08X mdio_addr1 0x%08X holdoff_quant 0x%08X tx_ipg_length 0x%08X Transmit Command 0x%08X Receive Command 0x%08X Multicast Hash[%02d] 0x%08X VRRS (Vmxnet3 Revision Report and Selection) 0x%x UVRS (UPT Version Report and Selection) 0x%x DSA (Driver Shared Address) 0x%08x%08x CMD (Command Register) 0x%x MAC (Media Access Control address) %02x:%02x:%02x:%02x:%02x:%02x ICR (Interrupt Cause Register) 0x%x ECR (Event Cause Register) 0x%x IMR (Interrupt Mask Register) %d 0x%x TXPROD (Transmit Ring Producer Register) 0x%x Base Address 0x%08x%08x Size %u next2fill %u next2comp %u gen %u Buffer Size %u Transmit Completion Ring size %u next2proc %u stopped %u RXPROD1 (Receive Ring Producer Register) 1 0x%x RXPROD2 (Receive Ring Producer Register) 2 0x%x Receive Completion Ring 0x0000: OWNER_EPID (Owner EPID) 0x%08X 0x0004: MAX_EP (Maximum EP) 0x%08X 0x0010: DCTL (Device Control) 0x%08X 0x0020: CR (Command request) 0x%08X 0x0024: CS (Command status) 0x%08X 0x0028: SHSTSAL (Share status address Low) 0x%08X 0x002C: SHSTSAH (Share status address High) 0x%08X 0x0034: REQBL (Request Buffer length) 0x%08X 0x0038: REQBAL (Request Buffer Address Low) 0x%08X 0x003C: REQBAH (Request Buffer Address High) 0x%08X 0x0044: RESPBL (Response Buffer Length) 0x%08X 0x0048: RESPBAL (Response Buffer Address Low) 0x%08X 0x004C: RESPBAH (Response Buffer Address High) 0x%08X 0x0080: IS (Interrupt status) 0x%08X 0x0084: IMS (Interrupt mask set) 0x%08X 0x0088: IMC (Interrupt mask clear) 0x%08X 0x008C: IG (Interrupt generator) 0x%08X 0x0090: ICTL (Interrupt control) 0x%08X Device identifier1 = 0x%04X Device identifier2 = 0x%04X Auto-Neg Advertisement = 0x%04X Auto-Neg Link Partner Ability = 0x%04X Auto-Neg Expansion = 0x%04X Auto-Neg Next Page TX = 0x%04X Auto-Neg Link Partner Next Page RX = 0x%04X MMD Access Control = 0x%04X MMD Access Address/Data = 0x%04X 1000BASE-T Status Extension1 = 0x%04X 1000BASE-TX Status Extension = 0x%04X 1000BASE-T Status Extension2 = 0x%04X 100BASE-TX/1000BASE-T Rx Error Counter = 0x%04X 100BASE-TX/1000BASE-T FC Err Counter = 0x%04X 10BASE-T/100BASE-TX/1000BASE-T LD Counter = 0x%04X Extended 10BASE-T Control and Status = 0x%04X Extended PHY Control1 = 0x%04X Extended PHY Control2 = 0x%04X Auxiliary Control and Status = 0x%04X Extended Page Access = 0x%04X Length too short, expected at least 0x%x Length is too short, expected 0x%zx %-41s : %.2f degrees C / %.2f degrees F %s near and far end limiting active equalizers%s far end limiting active equalizers%s near end limiting active equalizers %-41s : 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x Length (Copper or Active cable)Receiver signal average optical poweralarm/warning_flags_implementedAlarm/warning flags implemented Extended identifier description : High Power Class (> 3.5 W) enabled High Power Class (> 3.5 W) not enabled %-41s : 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x check failed FBNIC_CSR_START_INTR check failed FBNIC_CSR_END_INTR FBNIC_INTR_GLOBAL_IRQ_MSIX_CTL [31:31] MSIX_ENABLE: 0x%08x [07:00] MSIX_VECTOR: 0x%08x length failed FBNIC_CSR_END_INTR expected # segments in section %u actual # segments in section %u check failed FBNIC_CSR_START_INTR_CQ check failed FBNIC_CSR_END_INTR_CQ [13:00] RCQ_TIMEOUT: 0x%08x [13:00] TCQ_TIMEOUT: 0x%08x length failed FBNIC_CSR_END_INTR_CQ check failed FBNIC_CSR_START_QM_TX check failed FBNIC_CSR_END_QM_TX FBNIC_QM_TWQ_DEFAULT_META_L: 0x%08x FBNIC_QM_TWQ_DEFAULT_META_H: 0x%08x FBNIC_QM_TWQ_ERR_TYPE_INTR_MASK: 0x%08x [1:0] MASK_RD_AXI_ERRORS: 0x%08x [5:2] MASK_TWD_ERRORS: 0x%08x [6:6] PRE_FIFO_OVERFLOW: 0x%08x [7:7] PRE_FIFO_UNDERFLOW: 0x%08x [8:8] PRE_SINGLE_BIT: 0x%08x [9:9] PRE_DOUBLE_BIT: 0x%08x [10:10] MEM_SINGLE_BIT: 0x%08x [11:11] MEM_DOUBLE_BIT: 0x%08x [7:1] PRE_SPACE_THRESH: 0x%08x [8:8] TWD_ERROR_CHECK: 0x%08x [7:0] MC_FIFO_CRDTS: 0x%08x [15:8] BMC_FW_FIFO_CRDTS: 0x%08x FBNIC_QM_TQS_MTU_CTL0: 0x%08x [13:0] ETHERNET_MTU: 0x%08x FBNIC_QM_TQS_MTU_CTL1: 0x%08x FBNIC_QM_TQS_MTU_STS_0: 0x%08x [12:0] MC_FIFO_CRDT_USED: 0x%08x FBNIC_QM_TQS_MTU_STS_1: 0x%08x [12:0] BMC_FIFO_CRDT_USED: 0x%08x FBNIC_QM_TCQ_IDLE[%d]: 0x%08x FBNIC_QM_TCQ_ERR_INTR_STS[%d]: 0x%08x FBNIC_QM_TCQ_ERR_INTR_MASK[%d]: 0x%08x [15:0] TCQ_COAL_WAIT: 0x%08x [26:16] TICK_CYCLES: 0x%08x [15:0] ALMOST_FULL_THRESH: 0x%08x FBNIC_QM_TCQ_ERR_TYPE_INTR_MASK: 0x%08x [2:2] TCQ_ALMOST_FULL: 0x%02x [8:8] COAL_SINGLE_BIT: 0x%02x [9:9] COAL_DOUBLE_BIT: 0x%02x [10:10] MEM_SINGLE_BIT: 0x%02x [11:11] MEM_DOUBLE_BIT: 0x%02x [12:12] UNEXP_TCD_ERR: 0x%02x FBNIC_QM_TQS_IDLE[%d]: 0x%08x FBNIC_QM_TQS_ERR_INTR_STS[%d]: 0x%08x FBNIC_QM_TQS_ERR_INTR_MASK[%d]: 0x%08x FBNIC_QM_TQS_ERR_TYPE_INTR_MASK: 0x%08x [4:4] PRE_SINGLE_BIT: 0x%02x [5:5] PRE_DOUBLE_BIT: 0x%02x FBNIC_QM_TQS_EDT_TS_RANGE: 0x%08x FBNIC_QM_TQS_EDT_TS_BUCKET_CTL: 0x%08x FBNIC_QM_TQS_POS_DELTA_PKT[%d]: 0x%08x FBNIC_QM_TQS_NEG_TS_DELTA_PKT[%d]: 0x%08x FBNIC_QM_TDE_IDLE[%d]: 0x%08x FBNIC_QM_TDE_ERR_INTR_STS[%d]: 0x%08x FBNIC_QM_TDE_ERR_INTR_MASK[%d]: 0x%08x FBNIC_QM_TDE_ERR_TYPE_INTR_MASK: 0x%08x [1:0] RD_AXI_ERRORS: 0x%08x [3] TDF_NOCIF_IDLE_DP: 0x%02x [4] TDE_NOCIF_IDLE_DP: 0x%02x [5] TCM_NOCIF_IDLE_DP: 0x%02x FBNIC_QM_TNI_ERR_INTR_STS: 0x%08x [0] TDF_ROB_SINGLE_BIT: 0x%02x [1] TDF_ROB_DOUBLE_BIT: 0x%02x [2] TDE_ROB_SINGLE_BIT: 0x%02x [3] TDE_ROB_DOUBLE_BIT: 0x%02x [4] TCE_FIFO0_UNDRFLOW: 0x%02x [5] TCE_FIFO1_UNDRFLOW: 0x%02x FBNIC_QM_TNI_ERR_INTR_MASK: 0x%08x length failed FBNIC_CSR_END_QM_TX check failed FBNIC_CSR_START_QM_RX check failed FBNIC_CSR_END_QM_RX [15:00] RCD_COALESCE_WAIT: 0x%05x [26:16] TICK_CYCLES: 0x%05x [15:00] FULL_THRESH: 0x%08x FBNIC_QM_RCQ_ERR_INTR_MASK: 0x%02x [01:00] MASK_WR_AXI_ERRS: 0x%02x [02:02] MASK_RCQ_ALMOST_FULL: 0x%02x [08:08] COALESCE_SINGLE_BIT_ERR: 0x%02x [09:09] COALESCE_DOUBLE_BIT_ERR: 0x%02x [10:10] MEM_SINGLE_BIT_ERR: 0x%02x [11:11] MEM_DOUBLE_BIT_ERR: 0x%02x [12:12] UNEXPECTED_RCD: 0x%02x [15:00] ALMOST_EMPTY_THRESH: 0x%05x [31:16] PREFETCH_SPACE_THRESH: 0x%05x FBNIC_QM_BDQ_CTL0_ERR_INTR_MASK [00:00] MASK_BDQ_ALMOST_EMPTY: 0x%02x [02:01] MASK_RD_AXI_ERRS: 0x%02x [06:06] MASK_PRE_FIFO_OVERFLOW: 0x%02x [07:07] MASK_PRE_FIFO_UNDERFLOW: 0x%02x [08:08] MASK_PRE_SINGLE_BIT: 0x%02x [09:09] MASK_PRE_DOUBLE_BIT: 0x%02x [10:10] MASK_MEM_SINGLE_BIT: 0x%02x [11:11] MASK_MEM_DOUBLE_BIT: 0x%02x [15:00] DROP_WAIT_TIME: 0x%05x [21:16] RCD_DROP_THRESH: 0x%05x [25:22] HPQ_DROP_THRESH: 0x%05x [31:26] PPQ_DROP_THRESHOLD: 0x%05x FBNIC_QM_RDE_DMA_HINT_CTL: 0x%08x [05:00] L4_PAYLOAD_BYTES0: 0x%05x [11:06] L4_PAYLOAD_BYTES1: 0x%05x [17:12] L4_PAYLOAD_BYTES2: 0x%05x [23:18] L4_PAYLOAD_BYTES3: 0x%05x FBNIC_QM_RDE_ERR_INTR_STS[%d]: 0x%08x FBNIC_QM_RDE_ERR_INTR_MASK[%d]: 0x%08x FBNIC_QM_RDE_ERR_TYPE_INTR_MASK: 0x%08x [01:00] WR_AXI_ERRS: 0x%02x [02:02] CONTEXT_MEM_SINGLE_BIT: 0x%02x [03:03] CONTEXT_MEM_DOUBLE_BIT: 0x%02x [00:00] RBP_NOCIF_IDLE: 0x%02x [01:01] RDE_NOCIF_IDLE: 0x%02x [02:02] RCM_NOCIF_IDLE: 0x%02x [03:03] RBP_NOCIF_IDLE_DP: 0x%02x [04:04] RDE_NOCIF_IDLE_DP: 0x%02x [02:02] RCM_NOCIF_IDLE_DP: 0x%02x FBNIC_QM_RNI_ERR_INTR_STS: 0x%08x [0:0] RBP_SINGLE_BIT: 0x%02x [01:01] RBP_DOUBLE_BIT: 0x%02x FBNIC_QM_RNI_ERR_INTR_MASK: 0x%08x length failed FBNIC_CSR_END_QM_RX check failed FBNIC_CSR_START_TCE check failed FBNIC_CSR_END_TCE [08:00] TCP_FLAG_CLR_0: 0x%05x [17:09] TCP_FLAG_CLR_1: 0x%05x [26:18] TCP_FLAG_CLR_2: 0x%05x [27:27] IPV4_ID_MODE: 0x%05x [28:28] IPV4_ZERO_CSUM_ALLOWED: 0x%05x [00:00] TCP_ZERO_CSUM_ALLOWED: 0x%08x [01:01] TCAM_ENABLE: 0x%02x FBNIC_TCE_TXB_ENQ_WRR_CTRL: 0x%08x FBNIC_TCE_TXB_TEI_Q0_CTRL: 0x%08x FBNIC_TCE_TXB_TEI_Q1_CTRL: 0x%08x FBNIC_TCE_TXB_MC_Q_CTRL: 0x%08x FBNIC_TCE_TXB_RX_TEI_Q_CTRL: 0x%08x FBNIC_TCE_TXB_RX_BMC_Q_CTRL: 0x%08x FBNIC_TCE_TXB_TEI_DWRR_CTRL: 0x%08x FBNIC_TCE_TXB_NTWRK_DWRR_CTRL: 0x%08x FBNIC_TCE_TXB_CLDR_CFG: 0x%08x [01:00] DEST_ID_0_0: 0x%02x [03:02] DEST_ID_0_1: 0x%02x [05:04] DEST_ID_0_2: 0x%02x [07:06] DEST_ID_0_3: 0x%02x [09:08] DEST_ID_1_0: 0x%02x [11:10] DEST_ID_1_1: 0x%02x [13:12] DEST_ID_1_2: 0x%02x [15:14] DEST_ID_1_3: 0x%02x [17:16] DEST_ID_2_0: 0x%02x [19:18] DEST_ID_2_1: 0x%02x [21:20] DEST_ID_2_2: 0x%02x [23:22] DEST_ID_2_3: 0x%02x [25:24] DEST_ID_3_0: 0x%02x [27:26] DEST_ID_3_1: 0x%02x [29:28] DEST_ID_3_2: 0x%02x [31:30] DEST_ID_3_3: 0x%02x [00:00] TXB_DATA_FIFO_TX_Q0_OVFL: 0x%02x [01:01] TXB_DATA_FIFO_TX_Q1_OVFL: 0x%02x [02:02] TXB_DATA_FIFO_MC_OVFL: 0x%02x [03:03] TXB_DATA_FIFO_RX_OVFL: 0x%02x [04:04] TXB_DATA_FIFO_RX_BMC_OVFL: 0x%02x [08:08] TXB_INTR_FIFO_TDE_OVFL: 0x%02x [09:09] TXB_INTR_FIFO_TEI_OVFL: 0x%02x [10:10] TXB_INTR_FIFO_BMC_OVFL: 0x%02x [16:16] TTI_QUIESCENCE_DET: 0x%02x [17:17] TBI_QUIESCENCE_DET: 0x%02x [24:24] TTI_CM_SOP_FIFO_OVFL: 0x%02x [25:25] TTI_FRAME_SOP_FIFO_OVFL: 0x%02x [26:26] TBI_SOP_FIFO_OVFL: 0x%02x FBNIC_TCE_TCE_INTR_MASK: 0x%08x FBNIC_TCE_TXB_INGR_FIFO_LEVEL: 0x%08x [07:00] TXB_TDE_FIFO_LEVEL: 0x%05x [15:08] TXB_TEI_FIFO_LVL: 0x%05x [23:16] TXB_BMC_FIFO_LVL: 0x%05x FBNIC_TCE_MAX_PKTSZ_CTRL0: 0x%08x [13:00] RBT_TX_MAX_PKT: 0x%05x [27:14] RBT_RX_MAX_PKT: 0x%05x FBNIC_TCE_MC_MAX_PKTSZ: 0x%08x [13:00] TMI_MAX_PKT: 0x%08x FBNIC_TCE_SOP_PROT_CTRL: 0x%08x [07:00] TBI_POP_THRESh: 0x%05x [14:08] TTI_FRAME_POP_THRESH: 0x%05x [18:15] TTI_CM_POP_THRESH: 0x%05x [00:00] TTI_CM_DROP_EN: 0x%02x [01:01] TTI_FRAME_DROP_EN: 0x%02x [02:02] TBI_DROP_EN: 0x%02x FBNIC_TCE_TTI_CM_DROP_PKTS: 0x%08x FBNIC_TCE_TTI_CM_DROP_BYTE_L: 0x%08x FBNIC_TCE_TTI_CM_DROP_BYTE_H: 0x%08x FBNIC_TCE_TTI_FRAME_DROP_PKTS: 0x%08x FBNIC_TCE_TTI_FRAME_DROP_BYTE_L: 0x%08x FBNIC_TCE_TTI_FRAME_DROP_BYTE_H: 0x%08x FBNIC_TCE_TBI_DROP_PKTS: 0x%08x FBNIC_TCE_TBI_DROP_BYTE_L: 0x%08x FBNIC_TCE_TBI_DROP_BYTE_H: 0x%08x FBNIC_TCE_TTI_QUIESCENCE_TIMER: 0x%08x FBNIC_TCE_TBI_QUIESCENCE_TIMER: 0x%08x FBNIC_TCE_TTI_TNI_SOP_PROT_FIFO: 0x%08x [07:00] TTI_CM_FIFO: 0x%05x [15:08] TTI_FRAME_FIFO: 0x%05x FBNIC_TCE_TXB_TCAM_IDX2DEST_MAP: 0x%08x FBNIC_TCE_TXB_TX_BMC_Q_CTRL: 0x%08x FBNIC_TCE_TXB_BMC_DWRR_CTRL: 0x%08x FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT: 0x%08x FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT: 0x%08x FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT: 0x%08x length failed FBNIC_CSR_END_TCE ncsi_mac_rx_pkts_65to127octetsncsi_mac_rx_pkts_128to255octetsncsi_mac_rx_pkts_256to511octetsncsi_mac_rx_pkts_512to1023octetsncsi_mac_rx_pkts_1024to1518octetsncsi_mac_rx_pkts_1519tomaxoctetsncsi_mac_tx_pkts_65to127octetsncsi_mac_tx_pkts_128to255octetsncsi_mac_tx_pkts_256to511octetsncsi_mac_tx_pkts_512to1023octetsncsi_mac_tx_pkts_1024to1518octetsncsi_mac_tx_pkts_1519tomaxoctetsTX_FILTER_ALL_VLAN_ETHERTYPES_BITTX_TCPIP_FILTER_FULL_SEARCH_RANGETX_TCPIP_FILTER_WILD_SEARCH_RANGETX_UDPIP_FILTER_FULL_SEARCH_RANGETX_UDPIP_FILTER_WILD_SEARCH_RANGETX_ETH_FILTER_FULL_SEARCH_RANGETX_ETH_FILTER_WILD_SEARCH_RANGEETHERNET_WILDCARD_SEARCH_LIMITLaser bias current high warningLaser bias current low warningModule temperature high warningModule temperature low warningLaser output power high warningLaser output power low warning66667 7875h6::l:L:<::99999l9L9,977777777777777777798888|8\8L88;r:;(;5;B;O;\;i;v;;;;;;:r::::::::::::::::;:::::::::::::::(;:::::::::::::::5;:::::::::::::::B;:::::::::::::::O;:::::::::::::::\;:::::::::::::::i;:::::::::::::::v;:::::::::::::::;:::::::::::::::;:::::::::::::::;:::::::::::::::;:::::::::::::::;::::::::::::::::]]\]Z] ppБxP ĝ0]Uϛ 8q ۜLr6zhƚ)EQɔ ߔ9 &Fc ח-hxЮЮЮЮЮЮЮЮ00000000w #޵T````(cpppppppp@@@@@@@@ݹd0000""t`AddddlTDDDD$$$$TԺԺԺԺd4$t$F $4DTdL\\\\\\\\\\\\\\\\TTTTllll\Dl$Dl 4\$4p??@@@@@@@$@>@?unspecifiedManchesterSONET Scrambled256B/257B (transcoded FEC-enablereserved or unknunknown or unspeFibre Channel Style 1 copperyle 2 copperFibre Channel coaxial headersFibreJackOptical pigtailMPO Parallel Optic - 2x16Copper pigtailNo separable conCS optical conneMini CS optical connector850 nm VCSEL1310 nm VCSEL1550 nm VCSEL1310 nm FP1310 nm DFB1550 nm DFB1310 nm EML1550 nm EMLOthers/Undefined1490 nm DFBGBIC not specified / not MOD_DEFGBIC/SFP defined by 2-wire inter10G Ethernet: 10G Base-LRM [SFF-8472 rev10.4 onwInfiniband: 1X SInfiniband: 1X LInfiniband: 1X CESCON: ESCON MMFESCON: ESCON SMFSONET: OC-192, sSONET: SONET reach specifier bitSONET: OC-48, loSONET: OC-48, intermediate reachSONET: OC-48, shSONET: OC-12, single mode, long ngle mode, interSONET: OC-12, shSONET: OC-3, single mode, long rgle mode, inter.SONET: OC-3, shoEthernet: BASE-PEthernet: BASE-BEthernet: 100BASEthernet: 1000BAFC: very long diFC: short distanFC: intermediateFC: long distancFC: medium distaFC: Shortwave laser, linear Rx (FC: Longwave lasFC: Electrical inter-enclosure (ntra-enclosure (ser w/o OFC (SN)ser with OFC (SLFC: Copper FC-BaFC: Twin Axial PFC: Twisted PairFC: Miniature CoFC: Video Coax (FC: Multimode, 6FC: Multimode, 5FC: Single Mode FC: 1200 MBytes/FC: 800 MBytes/sFC: 400 MBytes/sFC: 200 MBytes/sFC: 100 MBytes/sExtended: 100G AOC or 25GAUI C2M AOC with worst BER of 5x10^(-5)Extended: 100G Base-SR4 or 25GBaase-LR4 or 25GBaase-ER4 or 25GBaCC or 25GAUI C2M ACC with worst ase-CR4 or 25G BExtended: 25G BaExtended: 10Gbase-T with SFI electrical interfacBER of 10^(-12)Extended: 100GE-DWDM2 (DWDM transceiver using 2 wavelengths on a 1550 nm DWDM grid with a reach Extended: 100G 1550nm WDM (4 wave-T Short ReachExtended: 5GBASEExtended: 2.5GBAExtended: 40G SWExtended: 100G SExtended: 100G PExtended: 4WDM-10 MSA (10km version of 100G CWDM4 with same RS(528,514) FEC in hExtended: 4WDM-20 MSA (20km version of 100GBASE-LR4 with RS(528,514) FEC in hostExtended: 4WDM-40 MSA (40km reach with APD receiver and RS(528,514) FEC in host Extended: 100GBASE-DR (clause 140), CAUI-4 (no FExtended: 100G-FR or 100GBASE-FR1 (clause 140), CAUI-4 (no FEC)Extended: 100G-LR or 100GBASE-LRExtended: Active Copper Cable with 50GAUI, 100GAUI-2 or 200GAUI-4 C2M. Providing a worst BER of Optical Cable with 50GAUI, 100GAUI-2 or 200GAUI-4 C2M. Providing a worst BER of2.6x10-4 for ACC, 10-5 for AUI, 2.6x10-4 for ACC, 10-5 for AUI,Extended: 50GBASE-CR, 100GBASE-CR2, or 200GBASE-E-SR, 100GBASE-SE-FR or 200GBASEExtended: 200GBAExtended: 200G 1Extended: 64GFC Extended: 128GFC4/2/1G Rate_Sele8/4/2G Rx Rate_S8/4/2G Independent Rx & Tx Rate_8/4/2G Tx Rate_SSFF-8431 appendiSFF-8431 limitinRX_LOS implementTX_FAULT implemeTX_DISABLE impleRATE_SELECT implTunable transmitReceiver decision threshold implLinear receiver output implementPower level 2 reCooled transceivRetimer or CDR iPaging implementPower level 3 re1.5W max. Power consumption2.5W max. Power 3.5W max. Power CDR present in TNo CDR in TX,4.0W max. Power consumption,4.5W max. Power 5.0W max. Power 40G Ethernet: 40G Active Cable ((reserved or unk100G Ethernet: 100G AOC or 25GAUI C2M AOC with worst BER of 5x1000G Base-SR4 or 00G CWDM4 MSA wi00G PSM4 Paralle00G ACC or 25GAUI C2M ACC with w00G Base-CR4 or 25G Base-CR CA-L25G Ethernet: 254x10G Ethernet: G PSM4 Parallel Ethernet: G959.1 profile P1I1-2D1 (10709 MBd, 2k profile P1S1-2D2 (10709 MBd, 40 profile P1L1-2D2 (10709 MBd, 80G Base-T with SFI electrical intorst BER of 10^(100GE-DWDM2 (DWDM transceiver using 2 wavelengths on a 1550 nm DWDM grid with a reach up to 80 k100G 1550nm WDM (4 wavelengths)10GBASE-T Short Reach (30 meters4WDM-10 MSA (10km version of 100G CWDM4 with same RS(528,514) FEC in host system4WDM-20 MSA (20kGBASE-LR4 with RS(528,514) FEC i4WDM-40 MSA (40km reach with APD receiver and RS(528,514) FEC in100GBASE-DR (clause 140), CAUI-4100G-FR or 100GBASE-FR1 (clause 140), CAUI-4 (no100G-LR or 100GBASE-LR1 (clause Active Copper Cable with 50GAUI, 100GAUI-2 or 200GAUI-4 C2M. Providing a worst BER of 10-6 or beActive Optical Cable with 50GAUI, 100GAUI-2 or 200GAUI-4 C2M. Providing a worst BER of 10-6 or bER of 2.6x10-4 for ACC, 10-5 forBER of 2.6x10-4 for ACC, 10-5 for AUI, or below50GBASE-CR, 100GBASE-CR2, or 20050GBASE-SR, 100GBASE-SR2, or 20050GBASE-FR or 20200G 1550 nm PSM40G OTN (OTU3B/OFC: 1600 MBytes/Revision not speSFF-8436 Rev 4.8SFF-8636 Rev 1.3SFF-8636 Rev 1.4SFF-8636 Rev 1.5SFF-8636 Rev 2.0SFF-8636 Rev 2.5ModuleLowPwrModulePwrUpModuleReadyModulePwrDnModuleFaultNo fault detected / not supporteTEC runawayData memory corrProgram memory c?= AB>check failed FBNIC_CSR_START_RPC_RAM check failed FBNIC_CSR_END_RPC_RAM [30:30] RSS_CTXT_ID: 0x%08x [29:29] ACT_TBL_IDX_EN: 0x%08x [15:00] RSS_EN_MASK: 0x%08x FBNIC_RPC_RAM_INNER_IPSRC_TCAM0_0length failed FBNIC_CSR_END_RPC_RAM check failed FBNIC_CSR_START_TCE_RAM check failed FBNIC_CSR_END_TCE_RAM length failed FBNIC_CSR_END_TCE_RAM check failed FBNIC_CSR_START_TMI check failed FBNIC_CSR_END_TMI FBNIC_TMI_SOP_PROT_CTRL: 0x%08x [07:00] POP_THRESHOLD: 0x%05x FBNIC_TMI_DROP_BYTE_L: 0x%08x FBNIC_TMI_DROP_BYTE_H: 0x%08x FBNIC_TMI_QUIESCENCE_TIMER: 0x%08x [00:00] QUIESCENCE_DET: 0x%02x [08:08] PTP_ERR_DET: 0x%02x [16:16] PTP_REQ_Q_OVFL: 0x%02x [17:17] PTP_RESP_Q_OVFL: 0x%02x [18:18] TDE_CMPL_OVFL: 0x%02x [24:24] SOP_PROT_OVFL: 0x%02x [25:25] SOP_PROT_ECC_MBE: 0x%02x [26:26] SOP_PROT_ECC_SBE: 0x%02x FBNIC_TMI_ILLEGAL_PTP_REQS: 0x%08x FBNIC_TMI_GOOD_PTP_TS: 0x%08x FBNIC_TMI_SOP_PROT_FIFO_LEVEL: 0x%08x [10:08] PKT_BUF_LEVEL: 0x%05x FBNIC_TMI_PTP_Q_LEVEL: 0x%08x [06:00] REQ_Q_LEVEL: 0x%05x [11:07] CMPL_Q_LEVEL: 0x%05x FBNIC_TMI_PAUSE_DURATION_H: 0x%08x FBNIC_TMI_PAUSE_DURATION_L: 0x%08x FBNIC_TMI_PERF_STATS_64B_U_WIN0FBNIC_TMI_PERF_STATS_64B_L_WIN0FBNIC_TMO_PERF_STATS_ITER_CNT_WIN0: 0x%08x FBNIC_TMI_PERF_STATS_64B_U_WIN1FBNIC_TMI_PERF_STATS_64B_L_WIN1FBNIC_TMO_PERF_STATS_ITER_CNT_WIN1: 0x%08x FBNIC_TMI_TX_PKT_1_64_L: 0x%08x FBNIC_TMI_TX_PKT_1_64_H: 0x%08x FBNIC_TMI_TX_PKT_65_127_L: 0x%08x FBNIC_TMI_TX_PKT_65_127_H: 0x%08x FBNIC_TMI_TX_PKT_128_255_L: 0x%08x FBNIC_TMI_TX_PKT_128_255_H: 0x%08x FBNIC_TMI_TX_PKT_256_511_L: 0x%08x FBNIC_TMI_TX_PKT_256_511_H: 0x%08x FBNIC_TMI_TX_PKT_512_1023_L: 0x%08x FBNIC_TMI_TX_PKT_512_1023_H: 0x%08x FBNIC_TMI_TX_PKT_1024_1518_L: 0x%08x FBNIC_TMI_TX_PKT_1024_1518_H: 0x%08x FBNIC_TMI_TX_PKT_1519_2047_L: 0x%08x FBNIC_TMI_TX_PKT_1519_2047_H: 0x%08x FBNIC_TMI_TX_PKT_2048_4095_L: 0x%08x FBNIC_TMI_TX_PKT_2048_4095_H: 0x%08x FBNIC_TMI_TX_PKT_4096_8191_L: 0x%08x FBNIC_TMi_TX_PKT_4096_8191_H: 0x%08x FBNIC_TMI_TX_PKT_8192_9216_L: 0x%08x FBNIC_TMI_TX_PKT_8192_9216_H: 0x%08x FBNIC_TMI_TX_PKT_9217_MAX_L: 0x%08x FBNIC_TMI_TX_PKT_9217_MAX_H: 0x%08x length failed FBNIC_CSR_END_TMI check failed FBNIC_CSR_START_PTP check failed FBNIC_CSR_END_PTP [04:04] MONOTONIC_EN: 0x%02x [08:08] TQS_OUTPUT_EN: 0x%02x [16:12] MAC_OUTPUT_INTER: 0x%02x [23:20] PTP_TICK_INTER: 0x%02x FBNIC_PTP_NUDGE_SUBNS: 0x%08x FBNIC_PTP_ADD_VAL_SUBNS: 0x%08x FBNIC_PTP_MONO_PTP_CTR_HI: 0x%08x FBNIC_PTP_MONO_PTP_CTR_LO: 0x%08x FBNIC_PTP_CDC_FIFO_STATUS: 0x%08x [03:00] RX_FILL_LEVEL: 0x%02x [08:08] RX_OFLOW_ERR: 0x%02x [19:16] TX_FILL_LEVEL: 0x%02x [24:24] TX_OFLOW_ERR: 0x%02x length failed FBNIC_CSR_END_PTP check failed FBNIC_CSR_START_RXB check failed FBNIC_CSR_END_RXB [05:00] HEADER_THRESH: 0x%05x [11:06] PAYLOAD_THRESH: 0x%05x [12:12] CUT_THROUGH: 0x%05x FBNIC_RXB_PAUSE_DROP_CTRL: 0x%08x [07:00] DROP_ENABLE: 0x%05x [15:08] PAUSE_ENABLE: 0x%05x [19:00] DET_TIME_THRESH: 0x%08x [20:20] FORCE_NORMAL: 0x%02x [02:00] REDIRECT_ENABLE: 0x%02x FBNIC_RXB_DWRR_RDE_WEIGHT0: 0x%08x FBNIC_RXB_DWRR_RDE_WEIGHT1: 0x%08x FBNIC_RXB_DWRR_BMC_WEIGHT: 0x%08x FBNIC_RXB_DWRR_REI_WEIGHT: 0x%08x FBNIC_RXB_CLDR_SLT_EN: 0x%08x [01:00] DST_SLOT0_PRI0: 0x%02x [03:02] DST_SLOT0_PRI1: 0x%02x [05:04] DST_SLOT0_PRI2: 0x%02x [07:06] DST_SLOT0_PRI3: 0x%02x [09:08] DST_SLOT1_PRI0: 0x%02x [11:10] DST_SLOT1_PRI1: 0x%02x [13:12] DST_SLOT1_PRI2: 0x%02x [15:14] DST_SLOT1_PRI3: 0x%02x [17:16] DST_SLOT2_PRI0: 0x%02x [19:18] DST_SLOT2_PRI1: 0x%02x [21:20] DST_SLOT2_PRI2: 0x%02x [23:22] DST_SLOT2_PRI3: 0x%02x [25:24] DST_SLOT3_PRI0: 0x%02x [27:26] DST_SLOT3_PRI1: 0x%02x [29:28] DST_SLOT3_PRI2: 0x%02x [31:30] DST_SLOT3_PRI3: 0x%02x [03:00] ENA_FCS_REMOVAL: 0x%02x [07:04] ENA_ENDIAN_CONV: 0x%02x [11:08] ENA_ENDIAN_16BYTE: 0x%02x [15:12] ENA_ENDIAN_8BYTE: 0x%02x [19:16] ENA_ENDIAN_4BYTE: 0x%02x [23:20] ENA_ENDIAN_2BYTE: 0x%02x [27:24] ENA_ENDIAN_1BYTE: 0x%02x [31:28] ENA_ENDIAN_BIT: 0x%02x FBNIC_RXB_ERR_INTR_STS: 0x%08x [07:00] DRBO_FRM_TRUN: 0x%05x [11:08] DRBO_DST_VEC: 0x%05x [15:12] PAUSE_STORM: 0x%05x [23:20] RPC_INTEGRITY: 0x%05x FBNIC_RXB_ERR_INTR_MASK: 0x%08x FBNIC_RXB_INTR_PAUSE_STORM_STSFBNIC_RXB_PAUSE_STORM_UNIT_RD: 0x%08x FBNIC_RXB_INTF_CREDIT_RD: 0x%08x [31:28] CUR_CREDIT_3: 0x%08x [27:24] CUR_CREDIT_2: 0x%08x [23:20] CUR_CREDIT_1: 0x%08x [19:16] CUR_CREDIT_0: 0x%08x FBNIC_RXB_PBUF_Q_OVFL: 0x%08x FBNIC_RXB_PBUF_Q_EMPTY: 0x%08x FBNIC_RXB_DRB_Q_EMPTY: 0x%08x FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT: 0x%08x FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT: 0x%08x FBNIC_RXB_DWRR_BMC_WEIGHT_EXT: 0x%08x FBNIC_RXB_DWRR_REI_WEIGHT_EXT: 0x%08x FBNIC_RXB_PBUF_Q_XOFF: 0x%08x [07:00] PBUF_FIFO_XOFF: 0x%05x FBNIC_RXB_PERF_STATS_64B_WIN0_HFBNIC_RXB_PERF_STATS_64B_WIN0_LFBNIC_RXB_PERF_STATS_ITER_CNT_WIN0: 0x%08x FBNIC_RXB_PERF_STATS_64B_WIN1_HFBNIC_RXB_PERF_STATS_64B_WIN1_LFBNIC_RXB_PERF_STATS_ITER_CNT_WIN1: 0x%08x FBNIC_RXB_Q_ECC_ERR_INTR_STS: 0x%08x [08:08] PBUF_CTRL_MBE: 0x%08x [09:09] PBUF_CTRL_SBE: 0x%08x [10:10] PBUF_DATA_MBE: 0x%08x [11:11] PBUF_CTRL_SBE: 0x%08x FBNIC_RXB_Q_ECC_ERR_INTR_MASK: 0x%08x FBNIC_RXB_PBUF_Q_OVFL_INTR_STS: 0x%08x FBNIC_RXB_DRB_Q_OVFL_INTR_SET: 0x%08x FBNIC_RXB_DRB_Q_OVFL_INTR_MASK: 0x%08x FBNIC_RXB_DRB_Q_UNFL_INTR_STS: 0x%08x [11:00] DRB1_FIFO_UNFL: 0x%08x [17:12] DRBO_FIFO_UNFL: 0x%08x [23:18] INTF_FIFO_UNFL: 0x%08x FBNIC_RXB_DRB_Q_UNFL_INTR_MASK: 0x%08x FBNIC_RXB_TOP_INTR_STS: 0x%08x [01:01] FIFO_ECC_ERR0R: 0x%08x [02:02] PBUF_FIFO_OVFL: 0x%08x [03:03] PBUF_FIFO_UNFL: 0x%08x [04:04] DRB_FIFO_OVFL: 0x%08x [05:05] DRB_FIFO_UNFL: 0x%08x FBNIC_RXB_PBUF_MC_CNT: 0x%08x length failed FBNIC_CSR_END_RXB check failed FBNIC_CSR_START_RPC check failed FBNIC_CSR_END_RPC [04:00] OVRHEAD_BYTES: 0x%05x [08:08] FCS_PRESENT: 0x%05x [12:12] INPUT_ENABLE: 0x%05x FBNIC_RPC_TAG0_CONFIG: 0x%08x FBNIC_RPC_TAG1_CONFIG: 0x%08x FBNIC_RPC_TAG2_CONFIG: 0x%08x FBNIC_RPC_TAG3_CONFIG: 0x%08x FBNIC_RPC_TCP_OPT_CONFIG: 0x%08x FBNIC_RPC_L4_WORD_OFF_0_1: 0x%08x [06:00] L4_WORD_OFF0: 0x%05x [07:07] L4_WORD_OFF0_VLD: 0x%05x [14:08] L4_WORD_OFF1: 0x%05x [15:15] L4_WORD_OFF1_VLD: 0x%05x FBNIC_RPC_L4_WORD_OFF_2_3: 0x%08x [06:00] L4_WORD_OFF2: 0x%05x [07:07] L4_WORD_OFF2_VLD: 0x%05x [14:08] L4_WORD_OFF3: 0x%05x [15:15] L4_WORD_OFF3_VLD: 0x%05x FBNIC_RPC_L4_WORD_OFF_4_5: 0x%08x [06:00] L4_WORD_OFF4: 0x%05x [07:07] L4_WORD_OFF4_VLD: 0x%05x [14:08] L4_WORD_OFF5: 0x%05x [15:15] L4_WORD_OFF5_VLD: 0x%05x FBNIC_RPC_RSS_BYTE_OFF: 0x%08x [07:00] RSS_BYTE_OFF: 0x%08x FBNIC_RPC_ACT_TBL0_DEFAULT: 0x%08x [30:30] RSS_CTXT_ID: 0x%02x FBNIC_RPC_ACT_TBL1_DEFAULT: 0x%08x [05:00] REMAPPED_DSCP: 0x%05x [00:00] OUT_OF_HDR_DETECT: 0x%02x [01:01] TCP_OPT_ERR: 0x%02x FBNIC_RPC_IPV6_EXT_TYPES0: 0x%08x FBNIC_RPC_IPV6_EXT_TYPES1: 0x%08x FBNIC_RPC_IPV6_EXT_TYPES_EN: 0x%08x FBNIC_RPC_CNTR_TCP_OPT_ERR: 0x%08x FBNIC_RPC_CNTR_UNKN_ETYPE: 0x%08x FBNIC_RPC_CNTR_IPV4_FRAG: 0x%08x FBNIC_RPC_CNTR_IPV6_FRAG: 0x%08x FBNIC_RPC_CNTR_IPV4_ESP: 0x%08x FBNIC_RPC_CNTR_IPV6_ESP: 0x%08x FBNIC_RPC_CNTR_UNKN_EXT_HDR: 0x%08x FBNIC_RPC_CNTR_OUT_OF_HDR_ERR: 0x%08x FBNIC_RPC_CNTR_OVR_SIZE_ERR: 0x%08x FBNIC_RPC_TCAM_MACDA_MISS_CNT: 0x%08x FBNIC_RPC_TCAM_OUTER_IPSRC_MISS_CNT: 0x%08x FBNIC_RPC_TCAM_OUTER_IPDST_MISS_CNT: 0x%08x FBNIC_RPC_TCAM_MISS_CNTR_INNER_IPSRC: 0x%08x FBNIC_RPC_TCAM_MISS_CNTR_INNER_IPDST: 0x%08x FBNIC_RPC_TCAM_ACT_MISS_CNT: 0x%08x FBNIC_RPC_TCAM_OUTER_IPSRC_HIT_CNTFBNIC_RPC_TCAM_OUTER_IPDST_HIT_CNTFBNIC_RPC_TCAM_MACDA_VALIDATE: 0x%08x FBNIC_RPC_TCAM_OUTER_IPSRC_VALIDATE: 0x%08x FBNIC_RPC_TCAM_OUTER_IPDST_VALIDATE: 0x%08x FBNIC_RPC_TCAM_IPSRC_VALIDATE: 0x%08x FBNIC_RPC_TCAM_IPDST_VALIDATE: 0x%08x FBNIC_RPC_TCAM_ACT_VALIDATE_L: 0x%08x FBNIC_RPC_TCAM_ACT_VALIDATE_H: 0x%08x FBNIC_RPC_TCAM_ACT_UPDATE_L: 0x%08x FBNIC_RPC_TCAM_ACT_UPDATE_H: 0x%08x FBNIC_RPC_TCAM_ACT_UPDATE_TRIG: 0x%08x [00:00] RMI_FIFO_OVF: 0x%02x [04:04] RMI_FIFO_SBE: 0x%02x [08:08] RMI_FIFO_DBE: 0x%02x FBNIC_RPC_BUF_WATERMARKS: 0x%08x FBNIC_RPC_TESTBUS_CFG: 0x%08x FBNIC_RPC_TESTBUS_VAL: 0x%08x FBNIC_RPC_PERF_CNT_EN: 0x%08x FBNIC_RPC_RMI_CONFIG_EXT: 0x%08x FBNIC_RPC_CNTR_RMI_RUNT_PKT_DRP: 0x%08x FBNIC_RPC_MPLS_CONFIG: 0x%08x [00:00] DIS_MPLS_IP_GUESS: 0x%02x [01:01] USE_TAG_AS_L3: 0x%02x FBNIC_RPC_STAT_RX_PKT_1_64_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_1_64_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_65_127_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_65_127_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_128_255_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_128_255_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_256_511_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_256_511_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_512_1023_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_512_1023_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_1024_1518_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_1024_1518_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_1519_2047_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_1519_2047_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_2048_4095_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_2048_4095_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_4096_8191_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_4096_8191_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_8192_9216_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_8192_9216_H: 0x%08x FBNIC_RPC_STAT_RX_PKT_9217_MAX_L: 0x%08x FBNIC_RPC_STAT_RX_PKT_9217_MAX_H: 0x%08x length failed FBNIC_CSR_END_RPC check failed FBNIC_CSR_START_FAB check failed FBNIC_CSR_END_FAB [00:00] RQM_AR_Q_OFLOW: 0x%02x [01:01] RQM_AR_Q_UFLOW: 0x%02x [02:02] TQM_AR_Q_OFLOW: 0x%02x [03:03] TQM_AR_Q_UFLOW: 0x%02x [04:04] TDE_AR_Q_OFLOW: 0x%02x [05:05] TDE_AR_Q_UFLOW: 0x%02x [06:06] PCIE_AR_Q_OFLOW: 0x%02x [07:07] PCIE_AR_Q_UFLOW: 0x%02x [08:08] RQM_AW_Q_OFLOW: 0x%02x [09:09] RQM_AW_Q_UFLOW: 0x%02x [10:10] TQM_AW_Q_OFLOW: 0x%02x [11:11] TQM_AW_Q_UFLOW: 0x%02x [12:12] RDE_AW_Q_OFLOW: 0x%02x [13:13] RDE_AW_Q_UFLOW: 0x%02x [14:14] PCIE_AW_Q_OFLOW: 0x%02x [15:15] PCIE_AW_Q_UFLOW: 0x%02x [16:16] RQM_W_Q_OFLOW: 0x%02x [17:17] RQM_W_Q_UFLOW: 0x%02x [18:18] TQM_W_Q_OFLOW: 0x%02x [19:19] TQM_W_Q_UFLOW: 0x%02x [20:20] RDE_W_Q_OFLOW: 0x%02x [21:21] RDE_W_Q_UFLOW: 0x%02x [22:22] PCIE_W_Q_OFLOW: 0x%02x [23:23] PCIE_W_Q_UFLOW: 0x%02x FBNIC_FAB_AXI4_AR_SPACER_0_CFG: 0x%08x [15:00] SPACER_THRESH: 0x%05x [16:16] SPACER_MASK: 0x%05x FBNIC_FAB_AXI4_AR_SPACER_1_CFG: 0x%08x FBNIC_FAB_AXI4_AR_SPACER_2_CFG: 0x%08x FBNIC_FAB_AXI4_AR_ARB_CFG: 0x%08x [25:25] AR_FENCE_ENB: 0x%02x [26:26] AR_DROP_ENB: 0x%02x FBNIC_FAB_AXI4_AW_ARB_WEIGHT: 0x%08x FBNIC_FAB_AXI4_AW_ARB_THRESH: 0x%08x FBNIC_FAB_AXI4_AW_ARB_CFG: 0x%08x [17:17] AW_HALT_ENB: 0x%02x [18:18] AW_FENCE_ENB: 0x%02x [19:19] AW_DROP_ENB: 0x%02x FBNIC_FAB_AXI4_B_RDE_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_B_TQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_B_RQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_R_TDE_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_R_TQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_R_RQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_R_TDE_LAST_STATS: 0x%08x FBNIC_FAB_AXI4_R_TQM_LAST_STATS: 0x%08x FBNIC_FAB_AXI4_R_RQM_LAST_STATS: 0x%08x FBNIC_FAB_AXI4_AR_TDE_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_AR_TQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_AR_RQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_AW_RDE_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_AW_TQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_AW_RQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_W_RDE_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_W_TQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_W_RQM_BEAT_STATS: 0x%08x FBNIC_FAB_AXI4_W_RDE_LAST_STATS: 0x%08x FBNIC_FAB_AXI4_W_TQM_LAST_STATS: 0x%08x FBNIC_FAB_AXI4_W_RQM_LAST_STATS: 0x%08x FBNIC_FAB_FENCE_HALT_STATUS: 0x%08x [08:00] AR_IN_FLIGHT_CNT: 0x%05x [09:09] AR_FENCE_STAT: 0x%05x [22:16] AW_IN_FLIGHT_CNT: 0x%05x [23:23] AW_FENCE_STAT: 0x%05x [24:24] AW_HALT_STAT: 0x%05x length failed FBNIC_CSR_END_FAB check failed FBNIC_CSR_START_MASTER check failed FBNIC_CSR_END_MASTER FBNIC_MASTER_MASTER_CFG: 0x%08x [00:00] SINGLE_MODE: 0x%02x [02:02] BRESP_SQUELCH: 0x%02x [03:03] RRESP_SQUELCH: 0x%02x FBNIC_MASTER_SEMAPHORE_0_RO: 0x%08x FBNIC_MASTER_SEMAPHORE_1_RO: 0x%08x FBNIC_MASTER_SEMAPHORE_2_RO: 0x%08x FBNIC_MASTER_SEMAPHORE_3_RO: 0x%08x FBNIC_MASTER_SEMAPHORE_4_RO: 0x%08x FBNIC_MASTER_SEMAPHORE_5_RO: 0x%08x FBNIC_MASTER_SEMAPHORE_6_RO: 0x%08x FBNIC_MASTER_SEMAPHORE_7_RO: 0x%08x FBNIC_MASTER_DBG_AXI4_AR_ADDR: 0x%08x [23:00] DBG_AXI4_AR_ADDR: 0x%05x [24:24] DBG_AR_ERR_TYPE: 0x%02x [28:28] DBG_AR_ADDR_VLD: 0x%02x FBNIC_MASTER_DBG_AXI4_AW_ADDR: 0x%08x [23:00] DBG_AXI4_AW_ADDR: 0x%05x [25:24] DBG_AW_ERR_TYPE: 0x%02x [28:28] DBG_AW_ADDR_VLD: 0x%02x FBNIC_MASTER_INTR_STS: 0x%08x [00:00] CSR_AXI_ERR: 0x%02x [01:01] FIFO_UFLOW_ERR: 0x%02x [02:02] FIFO_OFLOW_ERR: 0x%02x FBNIC_MASTER_CSR_AXI_ERR_STS: 0x%08x [07:00] AW_RSP_TIMEOUT: 0x%05x [15:08] AR_RSP_TIMEOUT: 0x%05x [23:16] REQ_TIMEOUT: 0x%05x [27:27] AXI4_AW_DEC: 0x%02x [28:28] AXI4_AR_DEC: 0x%02x FBNIC_MASTER_CSR_AXI_ERR_MASK: 0x%08x FBNIC_MASTER_BRIDGE_ERR_STS: 0x%08x FBNIC_MASTER_BRIDGE_ERR_MASK: 0x%08x FBNIC_MASTER_Q_OFLOW_ERR_STS: 0x%08x [07:00] TGT_AW_RSP_FIFO: 0x%05x [23:16] TGT_REQ_FIFO: 0x%05x [24:24] B_RSP_STG_FIFO: 0x%02x [25:25] R_RSP_STG_FIFO: 0x%02x [26:26] AW_CNTX1_FIFO: 0x%02x [27:27] AW_CNTX0_FIFO: 0x%02x [28:28] AR_CNTX_FIFO: 0x%02x [30:30] AW_REQ_FIFO: 0x%02x [31:31] AR_REQ_FIFO: 0x%02x FBNIC_MASTER_Q_OFLOW_ERR_MASK: 0x%08x FBNIC_MASTER_Q_UFLOW_ERR_STS: 0x%08x FBNIC_MASTER_Q_UFLOW_ERR_MASK: 0x%08x FBNIC_MASTER_AXI_NOC_ERR_STS: 0x%08x [00:00] DBG_INTR_REQ: 0x%02x [01:01] DBG_ROB_SBE: 0x%02x FBNIC_MASTER_AXI_NOC_ERR_MASK: 0x%08x FBNIC_MASTER_AXI_NOC_ROB_R_CFG: 0x%08x FBNIC_MASTER_AXI_NOC_ROB_W_CFG: 0x%08x FBNIC_MASTER_AXI_NOC_ROB_STS: 0x%08x [24:12] RDP_IDLE_DP: 0x%02x [24:12] WDP_IDLE_DP: 0x%02x FBNIC_MASTER_STATS_TRIG_CFG0: 0x%08x [01:01] CNTR_CLR_WIN1: 0x%02x [02:02] ITER_CNTR_CLR_WIN1: 0x%02x [04:04] CNTR_CLR_WIN0: 0x%02x [05:05] ITER_CNTR_CLR_WIN0: 0x%02x FBNIC_MASTER_STATS_CTRL_CFG0: 0x%08x [03:03] WAIT_ON_INTR_CLR: 0x%02x FBNIC_MASTER_STATS_RST_DLY_CYC_U0: 0x%08x FBNIC_MASTER_STATS_RST_DLY_CYC_L0: 0x%08x FBNIC_MASTER_STATS_START_DLY_CYC_U0: 0x%08x FBNIC_MASTER_STATS_START_DLY_CYC_L0: 0x%08x FBNIC_MASTER_STATS_ACCUM_CYC_U0: 0x%08x FBNIC_MASTER_STATS_ACCUM_CYC_L0: 0x%08x FBNIC_MASTER_STATS_TS_VAL_NS_U0: 0x%08x FBNIC_MASTER_STATS_TS_VAL_NS_L0: 0x%08x FBNIC_MASTER_STATS_INTR_STS0: 0x%08x FBNIC_MASTER_STATS_CTRL_CFG1: 0x%08x FBNIC_MASTER_STATS_RST_DLY_CYC_U1: 0x%08x FBNIC_MASTER_STATS_RST_DLY_CYC_L1: 0x%08x FBNIC_MASTER_STATS_START_DLY_CYC_U1: 0x%08x FBNIC_MASTER_STATS_START_DLY_CYC_L1: 0x%08x FBNIC_MASTER_STATS_ACCUM_CYC_U1: 0x%08x FBNIC_MASTER_STATS_ACCUM_CYC_L1: 0x%08x FBNIC_MASTER_STATS_TS_VAL_NS_U1: 0x%08x FBNIC_MASTER_STATS_TS_VAL_NS_L1: 0x%08x FBNIC_MASTER_STATS_INTR_STS1: 0x%08x FBNIC_MASTER_STATS_INTR_MASK1: 0x%08x FBNIC_MASTER_CSR_SEL_CFG: 0x%08x FBNIC_MASTER_CSR_DATA_CAP: 0x%08x [00:00] DATA_CAP_TRIG: 0x%02x FBNIC_MASTER_CSR_SEL_VAL: 0x%08x [11:11] 1_SWAP_DWORDS: 0x%05x [23:23] 2_SWAP_DWORDS: 0x%02x [31:24] USER_DEFINED: 0x%02x FBNIC_MASTER_CSR_DATA0: 0x%08x FBNIC_MASTER_CSR_DATA1: 0x%08x FBNIC_MASTER_NOC_USOC_INST_ID0: 0x%08x FBNIC_MASTER_NOC_USOC_INST_ID1: 0x%08x FBNIC_MASTER_NOC_USOC_INST_ID2: 0x%08x FBNIC_MASTER_STATS_TS_MASK0: 0x%08x FBNIC_MASTER_STATS_TS_MASK1: 0x%08x FBNIC_MASTER_STATS_STS: 0x%08x [06:06] ACCUM_THRESH_REACHED0: 0x%02x [07:07] ACCUM_THRESH_REACHED1: 0x%02x [08:08] WAIT_FOR_RESTART0: 0x%02x [09:09] WAIT_FOR_RESTART1: 0x%02x [10:10] RESTART_TRIGGERS0: 0x%02x [11:11] RESTART_TRIGGERS1: 0x%02x [12:12] TS_MATCHED0: 0x%02x [13:13] TS_MATCHED1: 0x%02x [14:14] DELAY_THRESH0_REACHED: 0x%02x [15:15] DELAY_THRESH1_REACHED: 0x%02x FBNIC_MASTER_AXI_NOC_SPARE0: 0x%08x FBNIC_MASTER_AXI_NOC_SPARE1: 0x%08x FBNIC_MASTER_AXI_NOC_SPARE2: 0x%08x length failed FBNIC_CSR_END_MASTER check failed FBNIC_CSR_START_PCS check failed FBNIC_CSR_END_PCS FBNIC_PCS_CONTROL1_%d: 0x%08x [05:02] SPEED_SELECTION: 0x%02x [06:06] SPEED_ALWAYS: 0x%02x [13:13] SPEED_SELECT_ALWAYS: 0x%02x [01:01] LOW_POWER_ABILITY: 0x%02x [02:02] PCS_RECEIVE_LINK: 0x%02x [08:08] RX_LPI_ACTIVE: 0x%02x [09:09] TX_LPI_ACTIVE: 0x%02x FBNIC_PCS_DEVS_IN_PKG1_%d: 0x%08x FBNIC_PCS_DEVS_IN_PKG2_%d: 0x%08x FBNIC_PCS_CONTROL2_%d: 0x%08x [15:00] PKG_ID_MASK: 0x%05x FBNIC_PCS_EEE_CTRL_%d: 0x%08x FBNIC_PCS_WAKE_ERR_CNTR_0: 0x%08x FBNIC_PCS_WAKE_ERR_CNTR_1: 0x%08x FBNIC_PCS_BASER_STS1_%d: 0x%08x FBNIC_PCS_BASER_STS2_%d: 0x%08x FBNIC_PCS_SEED_B%d[0]: 0x%08x FBNIC_PCS_SEED_B%d[1]: 0x%08x FBNIC_PCS_BASER_CTRL_%d: 0x%08x [00:00] DATA_PATTERN_SEL: 0x%02x [01:01] SELECT_SQUARE: 0x%02x [02:02] RX_TESTPATTERN: 0x%02x [03:03] TX_TESTPATTERN: 0x%02x [07:07] SELECT_RANDOM: 0x%02x FBNIC_PCS_BASER_ERR_CNTR_%d: 0x%08x FBNIC_PCS_ERR_BLK_HOC_%d: 0x%08x [13:00] ERR_BLOCKS_CNTR: 0x%05x FBNIC_PCS_MLANE_ALIGN_STAT1_%d: 0x%08x [07:00] LANE_BLOCK_LOCK: 0x%05x [01:01] LANE_ALIGN_STS: 0x%02x FBNIC_PCS_MLANE_ALIGN_STAT2_%d: 0x%08x [11:00] LANE_BLOCK_LOCK: 0x%05x FBNIC_PCS_MLANE_ALIGN_STAT3_%d: 0x%08x [07:00] LANE_ALIGN_MLOCK: 0x%05x FBNIC_PCS_MLANE_ALIGN_STAT4_%d: 0x%08x FBNIC_PCS_BIP_ERR_LANE_%d[0]: 0x%08x [15:00] ERROR_COUNTER: 0x%05x FBNIC_PCS_BIP_ERR_LANE_%d[1]: 0x%08x FBNIC_PCS_LANE_MPNG_%d[0]: 0x%08x [04:00] LANE_MAPPING: 0x%05x FBNIC_PCS_LANE_MPNG_%d[1]: 0x%08x FBNIC_PCS_VEND_SCRATCH[%d]: 0x%08x [15:00] VENDOR_SCRATCH: 0x%05x FBNIC_PCS_VEND_CORE_REV[%d]: 0x%08x FBNIC_PCS_VEND_VL_INTVL[%d]: 0x%08x [15:00] MARKER_COUNTER: 0x%05x FBNIC_PCS_VEND_TXLANE_THRESH[%d]: 0x%08x [03:00] THRESHOLD_0: 0x%02x [07:04] THRESHOLD_1: 0x%02x [11:08] THRESHOLD_2: 0x%02x [15:12] THRESHOLD_3: 0x%02x FBNIC_PCS_VL%d_%d_CHAN[%d]: 0x%08x FBNIC_PCS_VEND_PCS_MODE_VL_CHAN[%d]: 0x%08x [00:00] ENABLE_CLAUSE49: 0x%02x [01:01] DISABLE_MLD: 0x%02x [04:04] ST_ENA_CLAUSE49: 0x%02x [05:05] ST_DISABLE_MLD: 0x%02x [06:06] ST_HI_BER25: 0x%02x [%0d:00] VL%d_%d_CHAN: 0x%05x length failed FBNIC_CSR_END_PCS check failed FBNIC_CSR_START_RSFEC check failed FBNIC_CSR_END_RSFEC [00:00] BYPASS_CRRECTION: 0x%02x [01:01] BYPASS_ERR_IND: 0x%02x [02:02] DEGRADE_ENABLE: 0x%02x [03:03] AM16_COPY_DIS: 0x%02x [10:10] TC_PAD_ALTER: 0x%02x [07:00] RSFEC_LANE_MAP: 0x%05x [15:00] SYMBLERR_LO: 0x%05x [15:00] SYMBLERR_HI: 0x%05x FBNIC_RSFEC_VEND_CTRL: 0x%08x FBNIC_RSFEC_VEND_INFO1: 0x%08x [04:04] ALIGN_STS_LH: 0x%02x [05:05] MARKER_CHECK_RST: 0x%02x [10:10] ALIGN_STS_LL: 0x%02x [00:00] FEC_ABILITY: 0x%02x [01:01] FEC_ERR_IND_ABILITY: 0x%02x [00:00] FEC_LOCKED_VL0: 0x%02x [01:01] FEC_LOCKED_VL1: 0x%02x [15:00] VL0_NCCW_LO: 0x%05x [15:00] VL1_NCCW_LO: 0x%05x [15:00] VL1_NCCW_HI: 0x%05x length failed FBNIC_CSR_END_RSFEC FBNIC_RPC_TCAM_ACT%s[%d][%d]: 0x%08x [28:28] MAC_TS_EN: 0x%08x [24:16] DMA_HINT: 0x%08x [15:08] HOST_QID: 0x%08x [04:04] HOST_Q_SEL: 0x%08x [03:01] DEST: 0x%08x [00:00] ACC_DROP: 0x%08x [31:16] MASK: 0x%08x [15:00] VALUE: 0x%08x FBNIC_RPC_TCAM_MACDAFBNIC_RPC_TCAM_IPSRCFBNIC_RPC_TCAM_IPDSTFBNIC_RPC_RSS_TBL [07:00] QID: 0x%08x FBNIC_TCE_RAM_TCAM1 [15:00] MASK: 0x%05x [31:16] VALUE: 0x%05x FBNIC_TCE_RAM_TCAM0FBNIC_TCE_RAM_TCAM2FBNIC_TCE_RAM_TCAM3 [02:00] DEST VALUE: 0x%02x [05:03] DEST MASK: 0x%02x [06:06] MCQ VALUE: 0x%02x [06:06] MCQ MASK: 0x%02x [31:31] MCQ MASK: 0x%02x FBNIC_TMI_DROP_CTRL: 0x%08x [00:00] DROP_EN: 0x%02x [01:01] CMPL_DIS: 0x%02x FBNIC_TMI_DROP_PKTS: 0x%08x FBNIC_TMI_INTR_STS: 0x%08x FBNIC_TMI_INTR_MASK: 0x%08x FBNIC_TMI_BAD_PTP_TS: 0x%08x [07:00] Q_LEVEL: 0x%05x FBNIC_TMI_PAUSE_REQS: 0x%08x FBNIC_TMI_PERF_STATS_32B_WIN0FBNIC_TMI_PERF_STATS_32B_WIN1FBNIC_TMI_SPARE0: 0x%08x FBNIC_TMI_SPARE1: 0x%08x FBNIC_TMI_SPARE2: 0x%08x FBNIC_PTP_CTRL: 0x%08x [00:00] PTP_CTR_EN: 0x%02x FBNIC_PTP_INIT_HI: 0x%08x FBNIC_PTP_INIT_LO: 0x%08x FBNIC_PTP_NUDGE_NS: 0x%08x FBNIC_PTP_ADD_VAL_NS: 0x%08x [15:00] NS: 0x%05x FBNIC_PTP_CTR_VAL_HI: 0x%08x FBNIC_PTP_CTR_VAL_LO: 0x%08x FBNIC_PTP_SPARE: 0x%08x FBNIC_RXB_CT_SIZE [23:16] ECN_ENABLE: 0x%05x [27:24] PS_ENABLE: 0x%05x FBNIC_RXB_PAUSE_THLD [12:00] ON_THRESH: 0x%05x [25:13] OFF_THRESH: 0x%05x FBNIC_RXB_DROP_THLDFBNIC_RXB_PAUSE_STORM_THLDFBNIC_RXB_ECN_THLDFBNIC_RXB_UC_TO_MC: 0x%08x FBNIC_RXB_PBUF_CFG [21:13] SIZE: 0x%05x [12:00] BASE_ADDR: 0x%05x [31:24] QUANTUM_3: 0x%05x [07:00] QUANTUM_4: 0x%08x [05:00] NUM_SLOT: 0x%05x FBNIC_RXB_CLDR_PRIO_CFGFBNIC_RXB_ENDIAN_FCS: 0x%08x FBNIC_RXB_OUTPUT_EN: 0x%08x [01:00] CMD_ENA_0: 0x%02x [03:02] CMD_ENA_1: 0x%02x [05:04] CMD_ENA_2: 0x%02x [07:06] CMD_ENA_3: 0x%02x FBNIC_RXB_OUTPUT_STS: 0x%08x [01:00] STS_ENA_0: 0x%02x [03:02] STS_ENA_1: 0x%02x [05:04] STS_ENA_2: 0x%02x [07:06] STS_ENA_3: 0x%02x [08:08] ERR_ENA_0: 0x%02x [09:09] ERR_ENA_1: 0x%02x [10:10] ERR_ENA_2: 0x%02x [11:11] ERR_ENA_3: 0x%02x [19:16] DRBI_FRM: 0x%05x [27:24] RPC_MAC: 0x%05x [31:28] RPC_PARSER: 0x%05x FBNIC_RXB_PAUSE_EVENT_CNTFBNIC_RXB_DROP_FRMS_STSFBNIC_RXB_DROP_BYTES_STS_LFBNIC_RXB_DROP_BYTES_STS_HFBNIC_RXB_TRUN_FRMS_STSFBNIC_RXB_TRUN_BYTES_STS_LFBNIC_RXB_TRUN_BYTES_STS_HFBNIC_RXB_TRANS_PAUSE_STSFBNIC_RXB_TRANS_DROP_STSFBNIC_RXB_TRANS_ECN_STSFBNIC_RXB_INTR_TRUN_STSFBNIC_RXB_INTR_MC_VEC_STSFBNIC_RXB_DRBO_FRM_CNT_SRCFBNIC_RXB_DRBO_BYTE_CNT_SRC_LFBNIC_RXB_DRBO_BYTE_CNT_SRC_HFBNIC_RXB_INTF_FRM_CNT_DSTFBNIC_RXB_INTF_BYTE_CNT_DST_LFBNIC_RXB_INTF_BYTE_CNT_DST_HFBNIC_RXB_PBUF_FRM_CNT_DSTFBNIC_RXB_PBUF_BYTE_CNT_DST_LFBNIC_RXB_PBUF_BYTE_CNT_DST_HFBNIC_RXB_PBUF_FIFO_LEVEL [13:00] FIFO_LEVEL: 0x%05x [13:00] UNIT_10US: 0x%05x FBNIC_RXB_PBUF_FIFO_CREDIT_RD [13:00] CREDIT: 0x%05x [27:14] CUR_CREDIT: 0x%05x [15:12] CREDIT_3: 0x%08x [11:08] CREDIT_2: 0x%08x [07:04] CREDIT_1: 0x%08x [03:00] CREDIT_0: 0x%08x FBNIC_RXB_INTEGRITY_ERRFBNIC_RXB_MAC_ERRFBNIC_RXB_PARSER_ERRFBNIC_RXB_FRM_ERR [07:00] CTRL: 0x%05x [15:08] DATA: 0x%05x FBNIC_RXB_DRB_Q_OVFL: 0x%08x [11:00] DRB1: 0x%05x [17:12] DRB0: 0x%05x [23:18] INTF: 0x%05x [31:24] QUANTUM3: 0x%05x [07:00] QUANTUM4: 0x%05x FBNIC_RXB_PERF_STATS_32B_WIN0FBNIC_RXB_PERF_STATS_32B_WIN1 [03:00] DRBI_MBE: 0x%08x [07:04] DRBI_SBE: 0x%08x [14:12] INTF_MBE: 0x%08x [17:15] INTF_SBE: 0x%08x [03:00] DRBI: 0x%08x [07:04] DRBO: 0x%08x [11:08] INTF: 0x%08x [0:0] ERR_INTR_STS: 0x%08x FBNIC_RXB_PBUF_FRM_256_DSTFBNIC_RXB_PBUF_FRM_128_DSTFBNIC_RXB_PBUF_FRM_64_DSTFBNIC_RXB_RXB_SPARE0: 0x%08x FBNIC_RXB_RXB_SPARE1: 0x%08x FBNIC_RXB_RXB_SPARE2: 0x%08x FBNIC_RPC_RMI_CONFIG: 0x%08x [31:16] MTU: 0x%05x [15:00] TPID: 0x%05x [18:16] LENGTH: 0x%05x [07:00] OPT0_KIND: 0x%05x [13:08] OPT0_LEN: 0x%05x [23:16] OPT1_KIND: 0x%05x [29:24] OPT1_LEN: 0x%05x [00:00] ACC_DROP: 0x%02x [03:01] DEST: 0x%02x [04:04] HOST_Q_SEL: 0x%02x [15:08] HOST_QID: 0x%05x [24:16] DMA_HINT: 0x%05x [28:28] MAC_TS_EN: 0x%02x FBNIC_RPC_RSS_KEY: %8x FBNIC_RPC_DSCP_TBLFBNIC_RPC_INNER_DSCP_TBLFBNIC_RPC_ERROR: 0x%08x [07:00] EH_TYPE3: 0x%05x [15:08] EH_TYPE2: 0x%05x [23:16] EH_TYPE1: 0x%05x [31:24] EH_TYPE0: 0x%05x [07:00] EH_TYPE7: 0x%05x [15:08] EH_TYPE6: 0x%05x [23:16] EH_TYPE5: 0x%05x [31:24] EH_TYPE4: 0x%05x [07:00] MATCH_EN: 0x%08x FBNIC_RPC_TCAM_MACDA_HIT_CNTFBNIC_RPC_TCAM_IPSRC_HIT_CNTFBNIC_RPC_TCAM_IPDST_HIT_CNTFBNIC_RPC_TCAM_ACT_HIT_CNT [07:00] MASTER_EN: 0x%05x [02:00] TCAM: 0x%05x [07:03] OLD_INDEX: 0x%05x [12:08] NEW_INDEX: 0x%05x FBNIC_RPC_CMAC_ERR_CNTRSFBNIC_RPC_INTR_STS: 0x%08x FBNIC_RPC_INTR_MASK: 0x%08x [04:00] RMI_FIFO: 0x%05x [05:00] SEL: 0x%05x [30:30] DBG_ENABLE: 0x%02x [31:31] CFG_ENABLE: 0x%02x [00:00] VALUE: 0x%08x [06:00] RUNT_LMT: 0x%08x FBNIC_RPC_RPC_SPARE0: 0x%08x FBNIC_RPC_RPC_SPARE1: 0x%08x FBNIC_RPC_RPC_SPARE2: 0x%08x FBNIC_FAB_INTR_STS: 0x%08x FBNIC_FAB_INTR_MASK: 0x%08x [07:00] RQM_WEIGHT: 0x%05x [15:08] TQM_WEIGHT: 0x%05x [23:16] TDE_WEIGHT: 0x%05x [24:24] ARB_AR_ENB: 0x%02x [23:16] RDE_WEIGHT: 0x%05x [23:00] THRESH_VAL: 0x%05x [15:00] ARB_AW_MTU: 0x%05x [16:16] ARB_AW_ENB: 0x%02x FBNIC_FAB_SPARE_0: 0x%08x [01:01] B_RSP_MODE: 0x%02x [01:00] SEMAPHORE: 0x%02x [03:03] BRIDGE_ERR: 0x%02x [04:04] NOC_ERR: 0x%02x [24:24] AXI_W: 0x%02x [25:25] AXI4_AR: 0x%02x [26:26] AXI4_AR: 0x%02x [07:00] SLVERR: 0x%05x [15:08] DECERR: 0x%05x FBNIC_MASTER_SPARE_0: 0x%08x FBNIC_MASTER_FENCE: 0x%08x [07:00] DATA: 0x%05x [29:29] W_REQ_FIFO: 0x%02x [02:02] ROB_MBE: 0x%02x [03:03] ROB_SBE: 0x%02x [04:04] ROB_DBE: 0x%02x [04:00] MASK: 0x%05x [01:00] MRRS: 0x%02x [03:02] CLS: 0x%02x [01:00] MPS: 0x%02x [03:02] MPS: 0x%02x [00:00] RDP_IDLE: 0x%02x [01:01] WDP_IDLE: 0x%02x [00:00] START_WIN1: 0x%02x [03:03] START_WIN0: 0x%02x [00:00] ENABLE: 0x%02x [01:01] MODE: 0x%02x [02:02] CONTINUOUS: 0x%02x [00:00] STATUS: 0x%02x [00:00] MASK: 0x%02x [00:00] DATA_CAP: 0x%02x [01:01] OVR_EM: 0x%02x [05:00] 1_MUX_SEL: 0x%05x [10:06] 1_SEL: 0x%05x [17:12] 2_MUX_SEL: 0x%05x [22:18] MOD_2_SEL: 0x%05x [15:00] SMB: 0x%05x [31:16] SM: 0x%05x [15:00] XBM0: 0x%05x [31:16] XBM1: 0x%05x [15:00] XBM2: 0x%05x [31:16] XBM3: 0x%05x [02:00] STATE0: 0x%02x [05:03] STATE1: 0x%02x [11:11] LOW_POWER: 0x%02x [14:14] LOOPBACK: 0x%02x [15:15] PCS_RESET: 0x%02x FBNIC_PCS_STS1_%d: 0x%08x [07:07] FAULT: 0x%02x [10:10] RX_LPI: 0x%02x [11:11] TX_LPI: 0x%02x FBNIC_PCS_DEV_ID0_0: 0x%08x [15:00] DEV_ID: 0x%05x FBNIC_PCS_DEV_ID0_1: 0x%08x FBNIC_PCS_DEV_ID1_0: 0x%08x FBNIC_PCS_DEV_ID1_1: 0x%08x FBNIC_PCS_SPEED_%d: 0x%08x [00:00] C10GETH: 0x%02x [01:01] C10PASS_TS: 0x%02x [02:02] C40G: 0x%02x [03:03] C100G: 0x%02x [04:04] C25G: 0x%02x [05:05] C25G: 0x%02x [00:00] CLAUSE22: 0x%02x [01:01] PMD_PMA: 0x%02x [02:02] WIS_PRES: 0x%02x [03:03] PCS_PRES: 0x%02x [04:04] PHY_XS: 0x%02x [05:05] DTE_XS: 0x%02x [06:06] TC_PRES: 0x%02x [13:13] CLAUSE22: 0x%02x [14:14] DEV1: 0x%02x [15:15] DEV2: 0x%02x [03:03] PCS_TYPE: 0x%02x FBNIC_PCS_STS2_%d: 0x%08x [00:00] C10G_R: 0x%02x [01:01] C10G_X: 0x%02x [02:02] C25G_W: 0x%02x [03:03] C25G_T: 0x%02x [04:04] C40G_R: 0x%02x [05:05] C100G_R: 0x%02x [06:06] C25G_R: 0x%02x [07:07] C50G_R: 0x%02x FBNIC_PCS_PKG_ID0_%d: 0x%08x FBNIC_PCS_PKG_ID1_%d: 0x%08x [00:00] LPI_FW: 0x%02x [06:06] EEE_10G: 0x%02x [08:08] FW_40G: 0x%02x [09:09] DS_40G: 0x%02x [10:10] FW_25G: 0x%02x [11:11] DS_25G: 0x%02x [12:12] FW_100G: 0x%02x [13:13] DS_100G: 0x%02x [14:14] FW_50G: 0x%02x [00:00] BLK_LOCK: 0x%02x [01:01] HIGH_BER: 0x%02x [12:12] RECV_LINK: 0x%02x [07:00] ERR_CNT: 0x%05x [13:08] BER_CNTR: 0x%05x [14:14] HIGH_BER: 0x%02x [15:15] BLK_LOCK: 0x%02x [15:00] SEED: 0x%02x [15:00] SEED: 0x%05x [15:00] ERR_CNTR: 0x%05x FBNIC_PCS_BER_HOC_%d: 0x%08x [15:00] BER_HOC: 0x%05x [15:15] PRESENT: 0x%02x [15:00] REVISION: 0x%05x [%0d:00] VL%d_%d: 0x%05x [02:02] HI_BER25: 0x%02x [03:03] HI_BER5: 0x%02x [07:07] ST_HI_BER5: 0x%02x FBNIC_RSFEC_CONTROL [08:08] KP_ENABLE: 0x%02x [09:09] TC_PAD_VAL: 0x%02x FBNIC_RSFEC_STATUSFBNIC_RSFEC_CCW_LO [15:00] CCW_LO: 0x%05x FBNIC_RSFEC_CCW_HI [15:00] CCW_HI: 0x%05x FBNIC_RSFEC_NCCW_LO [15:00] NCCW_LO: 0x%05x FBNIC_RSFEC_NCCW_HI [15:00] NCCW_HI: 0x%05x FBNIC_RSFEC_LMAPFBNIC_RSFEC_DEC_THRESH [07:00] DEC_THRESH: 0x%05x FBNIC_RSFEC_SYMBLERR_LOFBNIC_RSFEC_SYMBLERR_HI [00:00] AMPS_LOCK: 0x%02x FBNIC_FCFEC_FEC_ABILITYFBNIC_FCFEC_FEC_CTRL [00:00] EN_FEC: 0x%02x [01:01] EN_ERR_IND: 0x%02x FBNIC_FCFEC_FEC_STSFBNIC_FCFEC_VL0_CCW_LO [15:00] VL0_CCW_LO: 0x%05x FBNIC_FCFEC_VL0_NCCW_LOFBNIC_FCFEC_VL1_CCW_LO [15:00] VL1_CCW_LO: 0x%05x FBNIC_FCFEC_VL1_NCCW_LOFBNIC_FCFEC_CW_HI alaabLb|bX4ZWlZZZZ|[[|XXWWWWWWXXXLXXXX4X4X4XdWdWdW,\WW\\\\\]L]|]]] ^<^l^^^^,_\____`L`|```\cc gfftffeee\e,eyy:vhhhhhhhhhhhhhhhh|vw}hhhhhhhhhh(TpTpTpTpoooooooohhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhp>p>p>pr|}}}y1+5]]]]]]]]]]]]]||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}$}7}}ٕ}gW_)!LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLxxxxxxxxLLLLLLLLbbbbbbbb||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||b@1͕ŕgw6666666666666666<ՖՖGu mOՖ ;Weo[ !J< T\,̖l< ܕ|L\,LhH(8HXhx8آ(ȥHHHHЧH(x8HP8hȭ(Xخ(8hȯ(XȰذHhȴȶϾƿ-----2{--------------\\\\W----- X{--------------------------------------------------------------------------------------------------------------------------------------------------\\\\\\\\\\\\\\\\\\\\T<<<<\X`yyyyyyyyѺλC! 55555:555550555555555_55555`55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555=4\T|check failed FBNIC_CSR_START_MAC_MAC check failed FBNIC_CSR_END_MAC_MAC [15:08] CORE_VERSION: 0x%05x [31:16] CUSTOMER_REV: 0x%05x [08:08] PAUSE_IGNORE: 0x%02x [09:09] TX_ADDR_INS: 0x%02x [10:10] LOOPBACK_EN: 0x%02x [13:13] CNTL_FRAME_ENA: 0x%02x [14:14] RX_ERR_DISC: 0x%02x [17:17] NO_LGTH_CHECK: 0x%02x [18:18] RS_COL_CNT_EXT: 0x%02x [20:20] PAUSE_PFC_COMP: 0x%02x [23:23] TX_LOWP_ENA: 0x%02x [24:24] LOWP_RXEMPTY: 0x%02x [25:25] FLT_TX_STOP_DIS: 0x%02x [26:26] TX_FIFO_RST: 0x%02x [27:27] FLT_HDL_DIS: 0x%02x [28:28] TX_PAUSE_DIS: 0x%02x [29:29] RX_PAUSE_DIS: 0x%02x [30:30] SHORT_PREAMBLE: 0x%02x [31:31] NO_PREAMBLE: 0x%02x FBNIC_MAC_RX_FIFO_SEC: 0x%08x [15:00] RX_SEC_FULL: 0x%05x [31:16] RX_SEC_EMPTY: 0x%05x FBNIC_MAC_TX_FIFO_SEC: 0x%08x [15:00] TX_SEC_FULL: 0x%05x [31:16] TX_SEC_EMPTY: 0x%05x FBNIC_MAC_USX_PCH_CTRL: 0x%08x [01:01] CRC_REVERSE: 0x%02x [04:04] TX_FORCE_1S_PTP: 0x%02x [06:06] TX_TS_CAP_DIS: 0x%02x [07:07] TX_TSID_OVR: 0x%02x [09:08] TX_NOTS_PCH_MODE: 0x%02x [11:10] TX_TS_PCH_MODE: 0x%02x [16:16] RX_KEEP_PCH: 0x%02x [18:18] RX_NOPTP_USE_FRC: 0x%02x [19:19] RX_CRCERR_USE_FRC: 0x%02x [20:20] RX_SUBPORT_CHECK: 0x%02x [21:21] RX_CRC_CHECK: 0x%02x [22:22] RX_BADCRC_DISCARD: 0x%02x [23:23] RX_NOPCH_CRC_DIS: 0x%02x [24:24] RX_FWD_IDLE: 0x%02x [25:25] RX_FWD_RSVD: 0x%02x FBNIC_MAC_HASHTABLE_LOAD: 0x%08x [05:00] HASH_TABLE_ADDR: 0x%05x [08:08] ENABLE_MULTICAST_FRAME: 0x%02x FBNIC_MAC_MDIO_CFG_STS: 0x%08x [01:01] MDIO_READ_ERROR: 0x%02x [04:02] MDIO_HOLD_TIME_SETTING: 0x%02x [05:05] MDIO_DISABLE_PREAMBLE: 0x%02x [06:06] MDIO_CLAUSE45: 0x%02x [15:07] MDIO_CLOCK_DIVISOR: 0x%05x [31:31] MDIO_BUSY_GLB: 0x%02x [04:00] DEVICE_ADDR: 0x%05x [14:14] READ_ADDR_POST_INCREMENT: 0x%02x [15:15] NORMAL_READ_TRANSACTION: 0x%02x FBNIC_MAC_MDIO_REGADDR: 0x%08x [15:00] MDIO_REGADDR: 0x%05x [00:00] RX_LOC_FAULT: 0x%02x [01:01] RX_REM_FAULT: 0x%02x [07:07] RX_LINT_FAULT: 0x%02x [24:24] PCH_RX_SUBPORT_ERR: 0x%02x [25:25] PCH_RX_CRC_ERR: 0x%02x [26:26] PCH_RX_UNSUP: 0x%02x [27:27] PCH_RX_FRM_DROP: 0x%02x [31:28] PCH_RX_SUBPORT: 0x%02x FBNIC_MAC_TX_IPG_LENGTH: 0x%08x [00:00] TXIPG_DIC_DISABLE: 0x%02x [15:08] COMPENSATION_HI: 0x%05x [31:16] COMPENSATION: 0x%05x [16:16] DIS_RX_CRC_CHK: 0x%02x FBNIC_MAC_CRC_INV_MASK: 0x%08x FBNIC_MAC_CL01_PAUSE_QUANTA: 0x%08x [15:00] CL0_PAUSE_QUANTA: 0x%05x [31:16] CL1_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL23_PAUSE_QUANTA: 0x%08x [15:00] CL2_PAUSE_QUANTA: 0x%05x [31:16] CL3_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL45_PAUSE_QUANTA: 0x%08x [15:00] CL4_PAUSE_QUANTA: 0x%05x [31:16] CL5_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL67_PAUSE_QUANTA: 0x%08x [15:00] CL6_PAUSE_QUANTA: 0x%05x [31:16] CL7_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL01_QUANTA_THRESH: 0x%08x [15:00] CL0_QUANTA_THRESH: 0x%05x [31:16] CL1_QUANTA_THRESH: 0x%05x FBNIC_MAC_CL23_QUANTA_THRESH: 0x%08x [15:00] CL2_QUANTA_THRESH: 0x%05x [31:16] CL3_QUANTA_THRESH: 0x%05x FBNIC_MAC_CL45_QUANTA_THRESH: 0x%08x [15:00] CL4_QUANTA_THRESH: 0x%05x [31:16] CL5_QUANTA_THRESH: 0x%05x FBNIC_MAC_CL67_QUANTA_THRESH: 0x%08x [15:00] CL6_QUANTA_THRESH: 0x%05x [31:16] CL7_QUANTA_THRESH: 0x%05x FBNIC_MAC_RX_PAUSE_STS: 0x%08x [00:00] CF_FRM_SENT: 0x%02x FBNIC_MAC_TS_TIMESTAMP: 0x%08x [04:04] PAUSETIMERX8: 0x%02x [05:05] ONESTEP_ENA: 0x%02x [06:06] RX_PAUSE_BYPASS: 0x%02x [08:08] TX_MAC_RS_ERR: 0x%02x [09:09] TS_DELTA_MODE: 0x%02x [10:10] TS_DELAY_MODE: 0x%02x [11:11] TS_BINARY_MODE: 0x%02x [12:12] TS_UPD64_MODE: 0x%02x [16:16] RX_CNT_MODE: 0x%02x [17:17] PFC_PULSE_MODE: 0x%02x [18:18] PFC_LP_MODE: 0x%02x [19:19] PFC_LP_16PRI: 0x%02x FBNIC_MAC_CL89_PAUSE_QUANTA: 0x%08x [15:00] CL8_PAUSE_QUANTA: 0x%05x [31:16] CL9_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL1011_PAUSE_QUANTA: 0x%08x [15:00] CL10_PAUSE_QUANTA: 0x%05x [31:16] CL11_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL1213_PAUSE_QUANTA: 0x%08x [15:00] CL12_PAUSE_QUANTA: 0x%05x [31:16] CL13_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL1415_PAUSE_QUANTA: 0x%08x [15:00] CL14_PAUSE_QUANTA: 0x%05x [31:16] CL15_PAUSE_QUANTA: 0x%05x FBNIC_MAC_CL89_QUANTA_THRESH: 0x%08x [15:00] CL8_QUANTA_THRESH: 0x%05x [31:16] CL9_QUANTA_THRESH: 0x%05x FBNIC_MAC_CL1011_QUANTA_THRESH: 0x%08x [15:00] CL10_QUANTA_THRESH: 0x%05x [31:16] CL11_QUANTA_THRESH: 0x%05x FBNIC_MAC_CL1213_QUANTA_THRESH: 0x%08x [15:00] CL12_QUANTA_THRESH: 0x%05x [31:16] CL13_QUANTA_THRESH: 0x%05x FBNIC_MAC_CL1415_QUANTA_THRESH: 0x%08x [15:00] CL14_QUANTA_THRESH: 0x%05x [31:16] CL15_QUANTA_THRESH: 0x%05x length failed FBNIC_CSR_END_MAC_MAC FBNIC_MAC_REV: 0x%08x [07:00] CORE_REV: 0x%05x FBNIC_MAC_SCRATCH: 0x%08x [31:00] SCRATCH: 0x%05x FBNIC_MAC_CMD_CONF: 0x%08x [00:00] TX_ENA: 0x%02x [01:01] RX_ENA: 0x%02x [02:02] MACCC_RSV2: 0x%02x [03:03] MACCC_RSV3: 0x%02x [04:04] PROMIS_EN: 0x%02x [05:05] PAD_EN: 0x%02x [06:06] CRC_FWD: 0x%02x [07:07] PAUSE_FWD: 0x%02x [11:11] TX_PAD_EN: 0x%02x [12:12] SW_RESET: 0x%02x [15:15] PHY_TXENA: 0x%02x [16:16] SEND_IDLE: 0x%02x [19:19] PFC_MODE: 0x%02x [21:21] RX_SFD_ANY: 0x%02x [22:22] TX_FLUSH: 0x%02x FBNIC_MAC_ADDR_0: 0x%08x FBNIC_MAC_ADDR_1: 0x%08x [15:00] MAC_ADDR_1: 0x%05x FBNIC_MAC_FRM_LENGTH: 0x%08x [15:00] FRM_LENGTH: 0x%05x [31:16] TX_MTU: 0x%05x [00:00] PCH_ENA: 0x%02x [05:05] TX_PTP_DIS: 0x%02x [17:17] RX_PTP_DIS: 0x%02x [26:26] RX_DROP_FE: 0x%02x [31:28] SUBPORT: 0x%02x [00:00] MDIO_BUSY: 0x%02x FBNIC_MAC_MDIO_CMD: 0x%08x [09:05] PORT_ADDR: 0x%05x FBNIC_MAC_MDIO_DATA: 0x%08x [15:00] MDIO_DATA: 0x%05x FBNIC_MAC_STS: 0x%08x [02:02] PHY_LOS: 0x%02x [03:03] TS_AVAIL: 0x%02x [04:04] RX_LOWP: 0x%02x [05:05] TX_EMPTY: 0x%02x [06:06] RX_EMPTY: 0x%02x [08:08] TX_IS_IDLE: 0x%02x [05:03] TXIPG: 0x%02x FBNIC_MAC_CRC_MODE: 0x%08x [18:18] CRCSIZE_1: 0x%02x [19:19] CRCSIZE_2: 0x%02x [20:20] CRCSIZE_0: 0x%02x [15:00] PAUSESTS: 0x%05x FBNIC_MAC_CF_GEN_STS: 0x%08x FBNIC_MAC_XIF_MODE: 0x%08x [00:00] XGMII: 0x%02x [20:20] TS_SFD_ENA: 0x%02x $\4Գ4Գ|ԽԳ4ԻtTlD4ԶtT,check failed FBNIC_CSR_START_PCIE_SS_COMPHY check failed FBNIC_CSR_END_PCIE_SS_COMPHY FBNIC_PCIE_ANA_MISC_REG1: 0x%08x FBNIC_PCIE_ANA_SQ_REG0: 0x%08x FBNIC_PCIE_ANA_SQ_REG2: 0x%08x [02:02] SQ_THRESH_CAL_EN: 0x%02x FBNIC_PCIE_ANA_DATA_REG0: 0x%08x [03:03] LOCAL_ANA_TX2RX_LPBK_EN: 0x%02x FBNIC_PCIE_ANA_MISC_REG0: 0x%08x [02:02] TXCLK_ALIGN_EN: 0x%02x FBNIC_PCIE_ANA_TXCLK_DLY0: 0x%08x FBNIC_PCIE_PM_CTRL_TX_REG1: 0x%08x [21:21] RST_CORE_ACK_TX: 0x%02x [16:16] ANA_IDLE_SYNC_EN: 0x%02x FBNIC_PCIE_PM_CTRL_TX_REG2: 0x%08x [07:06] BEACON_EN_DELAY_1_0: 0x%02x FBNIC_PCIE_IN_TX_PIN_REG3: 0x%08x FBNIC_PCIE_CLKGEN_TX_REG1: 0x%08x [28:28] REFCLK_ON_DCLK_DIS: 0x%02x [07:07] SOC_LATENCY_REDUCE_EN: 0x%02x [05:03] TX_TRAIN_PAT_SEL_2_0: 0x%02x FBNIC_PCIE_TX_SPEED_CONVERT: 0x%08x [31:31] LOCAL_DIG_RX2TX_LPBK_EN: 0x%02x [18:18] TXD_MSB_LSB_SWAP: 0x%02x [05:05] TXDATA_MSB_LSB_SWAP: 0x%02x FBNIC_PCIE_TX_SYS_LN0: 0x%08x [29:29] TRX_TXCLK_SEL: 0x%02x [24:24] SSC_DSPREAD_TX: 0x%02x FBNIC_PCIE_TX_SYS_LN1: 0x%08x FBNIC_PCIE_TX_SYS_LN2: 0x%08x [11:11] SSC_AMP_UNIT_SEL: 0x%02x [10:00] SSC_AMP_20UNIT_10_0: 0x%05x [16:16] RX2TX_FREQ_TRAN_EN: 0x%02x FBNIC_PCIE_ALIGNMENT_REG1: 0x%08x [29:24] TESTBUS_SEL_HI0_5_0: 0x%05x [13:08] TESTBUS_SEL_LO0_5_0: 0x%05x FBNIC_PCIE_PHYTEST_TX0: 0x%08x [30:30] PT_TX_PHYREADY_FORCE: 0x%02x [29:24] PT_TX_PAT_SEL_5_0: 0x%05x [20:20] PT_TX_START_RD: 0x%02x [16:16] PT_TX_PRBS_ENC_EN: 0x%02x [15:11] SSPRQ_UI_DLY_CTRL_4_0: 0x%02x [04:04] TX_TRAIN_POLY_SEL_FM_PIN: 0x%02x [03:02] PT_TX_EN_MODE_1_0: 0x%02x FBNIC_PCIE_PHYTEST_TX1: 0x%08x FBNIC_PCIE_PHYTEST_TX2: 0x%08x FBNIC_PCIE_PHYTEST_TX3: 0x%08x [31:16] PT_TX_USR_PAT_15_0: 0x%05x [15:08] PT_TX_USR_K_CHAR_7_0: 0x%05x FBNIC_PCIE_PHYTEST_OOB_CTRL: 0x%08x [22:22] PT_TX_SATA_LONG: 0x%02x FBNIC_PCIE_TX_TRAINING_IF_REG1: 0x%08x [09:00] TX_TRAIN_PAT_9_0: 0x%05x FBNIC_PCIE_TX_TRAINING_IF_REG2: 0x%08x [01:01] TX_TRAIN_PAT_MODE: 0x%02x [00:00] TX_TRAIN_PAT_TOGGLE: 0x%02x FBNIC_PCIE_TX_TRAINING_IF_REG3: 0x%08x [31:31] TX_TRAIN_PAT_TWO_ZERO: 0x%02x [01:00] ETHERNET_MODE_TX_1_0: 0x%02x FBNIC_PCIE_TX_TRAINING_IF_REG4: 0x%08x [29:24] TX_FIR_C0_5_0: 0x%05x [22:17] TX_FIR_C1_5_0: 0x%05x [14:09] TX_FIR_C2_5_0: 0x%05x [06:01] TX_FIR_C3_5_0: 0x%05x FBNIC_PCIE_TX_TRAINING_IF_REG5: 0x%08x [30:25] TX_FIR_C4_5_0: 0x%05x [22:17] TX_FIR_C5_5_0: 0x%05x FBNIC_PCIE_TX_TRAINING_IF_REG7: 0x%08x [21:16] TO_ANA_TX_FIR_C5_5_0: 0x%05x FBNIC_PCIE_TX_TRAIN_REG0: 0x%08x [13:13] PCIE_GEN12_SEL: 0x%02x FBNIC_PCIE_TX_TRAIN_REG1: 0x%08x [23:23] TX_COE_FM_PIN_PCIE3_EN: 0x%02x FBNIC_PCIE_PM_CTRL_RX_REG1: 0x%08x [07:04] RX_SELMUFF_3_0: 0x%02x [03:00] RX_SELMUFI_3_0: 0x%02x [29:29] RX_EQ_PAM2_EN: 0x%02x [28:28] RX_ANA_PAM2_EN: 0x%02x [16:16] TRX_RXCLK_SEL: 0x%02x FBNIC_PCIE_CLKGEN_RX_REG1: 0x%08x [26:26] RST_FRAME_SYNC_DET_CLK: 0x%02x [02:02] RST_CORE_ACK_RX: 0x%02x FBNIC_PCIE_FRAME_SYNC_DET_REG0: 0x%08x [31:30] FRAME_DET_MIDD_LEVEL_1_0: 0x%02x [29:28] FRAME_DET_SIDE_LEVEL_1_0: 0x%02x [27:27] FRAME_LOCK_SEL: 0x%02x [26:24] GOOD_MARKER_2_0: 0x%02x [23:21] BAD_MARKER_2_0: 0x%02x [10:10] FRAME_REALIGN_MODE: 0x%02x [09:09] FRAME_DET_MODE: 0x%02x [08:08] ALIGN_STAT_RD_REQ: 0x%02x FBNIC_PCIE_RX_DATA_PATH_REG: 0x%08x [31:31] LOCAL_DIG_TX2RX_LPBK_EN: 0x%02x [27:27] RXD_MSB_LSB_SWAP: 0x%02x [26:26] SOC_LATENCY_REDUCE_EN: 0x%02x [24:24] RXDATA_MSB_LSB_SWAP: 0x%02x [26:24] DTL_CLAMPING_SEL_2_0: 0x%02x [23:23] DTL_CLAMPING_SCALE: 0x%02x [22:21] DTL_CLAMPING_RATIO_NEG_1_0: 0x%02x [16:16] RX_FOFFSET_RD_REQ: 0x%02x [15:15] SSC_DSPREAD_RX: 0x%02x [13:13] DTL_SQ_DET_EN: 0x%02x [31:31] RX_FOFFSET_RDY: 0x%02x [30:18] RX_FOFFSET_RD_12_0: 0x%05x [17:17] DTL_STEP_MODE: 0x%02x [16:16] RX_FOFFSET_DISABLE: 0x%02x [15:15] PIN_RX_SQ_OUT_RD: 0x%02x [14:14] PIN_RX_SQ_OUT_LPF_RD: 0x%02x [13:13] SQ_GATE_RXDATA_EN: 0x%02x [11:11] INT_SQ_LPF_EN: 0x%02x [08:08] SQ_DEGLITCH_EN: 0x%02x [07:04] SQ_DEGLITCH_WIDTH_N_3_0: 0x%02x [03:00] SQ_DEGLITCH_WIDTH_P_3_0: 0x%02x FBNIC_PCIE_PHYTEST_RX0: 0x%08x [31:30] PT_RX_EN_MODE_1_0: 0x%02x [29:24] PT_RX_PAT_SEL_5_0: 0x%05x [22:22] PT_RX_PHYREADY_FORCE: 0x%02x [21:21] PT_RX_CNT_RST: 0x%02x [20:20] PT_RX_CNT_PAUSE: 0x%02x [07:00] PT_RX_LOCK_CNT_7_0: 0x%05x FBNIC_PCIE_PHYTEST_RX1: 0x%08x FBNIC_PCIE_PHYTEST_RX2: 0x%08x FBNIC_PCIE_PHYTEST_RX3: 0x%08x [31:16] PT_RX_USR_PAT_15_0: 0x%05x [14:12] TX_TRAIN_PAT_SEL_RX_2_0: 0x%02x [11:11] PT_RX_START_RD: 0x%02x [10:10] PT_RX_SATA_LONG: 0x%02x [09:09] PT_RX_PRBS_ENC_EN: 0x%02x [02:02] PT_RX_CNT_READY: 0x%02x FBNIC_PCIE_PHYTEST_RX4: 0x%08x [31:16] PT_RX_CNT_47_32: 0x%05x FBNIC_PCIE_PHYTEST_RX5: 0x%08x FBNIC_PCIE_PHYTEST_RX6: 0x%08x [31:16] PT_RX_ERR_CNT_47_32: 0x%05x FBNIC_PCIE_PHYTEST_RX7: 0x%08x FBNIC_PCIE_PHYTEST_RX8: 0x%08x [31:16] PT_RX_CNT_MAX_47_32: 0x%05x FBNIC_PCIE_PHYTEST_RX9: 0x%08x FBNIC_PCIE_RX2PLL_REG: 0x%08x [24:24] RX2PLL_FREQ_TRAN_EN: 0x%02x FBNIC_PCIE_FRAME_SYNC_DET_REG5: 0x%08x [28:19] SYNC_CHAR_9_0: 0x%05x [18:09] SYNC_MASK_9_0: 0x%05x [03:03] PIPE_RX_SFT_RST_NO_REG: 0x%02x [02:02] SFT_RST_NO_REG_RX: 0x%02x [01:01] PIPE_TX_SFT_RST_NO_REG: 0x%02x [00:00] SFT_RST_NO_REG_TX: 0x%02x FBNIC_PCIE_MCU_MEM_REG2: 0x%08x [29:29] XDATA_MEM_CSUM_PASS: 0x%02x [28:28] XDATA_MEM_CSUM_RST: 0x%02x [27:27] IRAM_ECC_2ERR_SET: 0x%02x [26:26] CACHE_ECC_2ERR_SET: 0x%02x [25:25] XDATA_ECC_2ERR_SET: 0x%02x [24:24] IRAM_ECC_1ERR_SET: 0x%02x [23:23] CACHE_ECC_1ERR_SET: 0x%02x [22:22] XDATA_ECC_1ERR_SET: 0x%02x [21:21] IRAM_ECC_2ERR_CLR: 0x%02x [20:20] CACHE_ECC_2ERR_CLR: 0x%02x [19:19] XDATA_ECC_2ERR_CLR: 0x%02x [18:18] IRAM_ECC_1ERR_CLR: 0x%02x [17:17] CACHE_ECC_1ERR_CLR: 0x%02x [16:16] XDATA_ECC_1ERR_CLR: 0x%02x [15:15] IRAM_ECC_2ERR_EN: 0x%02x [14:14] CACHE_ECC_2ERR_EN: 0x%02x [13:13] XDATA_ECC_2ERR_EN: 0x%02x [12:12] IRAM_ECC_1ERR_EN: 0x%02x [11:11] CACHE_ECC_1ERR_EN: 0x%02x [10:10] XDATA_ECC_1ERR_EN: 0x%02x [09:09] IRAM_ECC_2ERR: 0x%02x [08:08] CACHE_ECC_2ERR: 0x%02x [07:07] XDATA_ECC_2ERR: 0x%02x [06:06] IRAM_ECC_1ERR: 0x%02x [05:05] CACHE_ECC_1ERR: 0x%02x [04:04] XDATA_ECC_1ERR: 0x%02x FBNIC_PCIE_MEM_ECC_ERR_ADDR0: 0x%08x [31:24] CACHE_ECC_ERR_ADDR_7_0: 0x%05x [23:16] IRAM_ECC_ERR_ADDR_7_0: 0x%05x [09:00] XDATA_ECC_ERR_ADDR_9_0: 0x%05x FBNIC_PCIE_XDATA_MEM_CSUM_LN0: 0x%08x FBNIC_PCIE_XDATA_MEM_CSUM_LN1: 0x%08x FBNIC_PCIE_DFE_CTRL_REG2: 0x%08x [15:00] DFE_UPDATE_EN_15_0: 0x%05x FBNIC_PCIE_DFE_STATIC_REG0: 0x%08x FBNIC_PCIE_DFE_FIR_REG0: 0x%08x [11:08] DFE_HP1_SM_3_0: 0x%02x [07:00] DFE_HP1_2C_7_0: 0x%05x FBNIC_PCIE_DFE_FIR_REG1: 0x%08x [11:08] DFE_HN1_SM_3_0: 0x%02x [07:00] DFE_HN1_2C_7_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_EVEN0: 0x%08x [30:24] DFE_DC_S_BOT_E_SM_6_0: 0x%05x [22:16] DFE_DC_D_TOP_E_SM_6_0: 0x%05x [14:08] DFE_DC_D_MID_E_SM_6_0: 0x%05x [06:00] DFE_DC_D_BOT_E_SM_6_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_EVEN1: 0x%08x [14:08] DFE_DC_S_TOP_E_SM_6_0: 0x%05x [06:00] DFE_DC_S_MID_E_SM_6_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_EVEN4: 0x%08x [30:24] DFE_F1_S_BOT_E_SM_6_0: 0x%05x [22:16] DFE_F1_D_TOP_E_SM_6_0: 0x%05x [14:08] DFE_F1_D_MID_E_SM_6_0: 0x%05x [06:00] DFE_F1_D_BOT_E_SM_6_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_EVEN5: 0x%08x [14:08] DFE_F1_S_TOP_E_SM_6_0: 0x%05x [06:00] DFE_F1_S_MID_E_SM_6_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_ODD0: 0x%08x [30:24] DFE_DC_S_BOT_O_SM_6_0: 0x%05x [22:16] DFE_DC_D_TOP_O_SM_6_0: 0x%05x [14:08] DFE_DC_D_MID_O_SM_6_0: 0x%05x [06:00] DFE_DC_D_BOT_O_SM_6_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_ODD1: 0x%08x [14:08] DFE_DC_S_TOP_O_SM_6_0: 0x%05x [06:00] DFE_DC_S_MID_O_SM_6_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_ODD4: 0x%08x [30:24] DFE_F1_S_BOT_O_SM_6_0: 0x%05x [22:16] DFE_F1_D_TOP_O_SM_6_0: 0x%05x [14:08] DFE_F1_D_MID_O_SM_6_0: 0x%05x [06:00] DFE_F1_D_BOT_O_SM_6_0: 0x%05x FBNIC_PCIE_DFE_READ_SM_REG_ODD5: 0x%08x [14:08] DFE_F1_S_TOP_O_SM_6_0: 0x%05x [06:00] DFE_F1_S_MID_O_SM_6_0: 0x%05x FBNIC_PCIE_EOM_ERR_REG00: 0x%08x FBNIC_PCIE_EOM_ERR_REG01: 0x%08x FBNIC_PCIE_EOM_ERR_REG02: 0x%08x FBNIC_PCIE_EOM_ERR_REG10: 0x%08x FBNIC_PCIE_EOM_ERR_REG11: 0x%08x FBNIC_PCIE_EOM_ERR_REG12: 0x%08x FBNIC_PCIE_EOM_VLD_REG00: 0x%08x FBNIC_PCIE_EOM_VLD_REG01: 0x%08x FBNIC_PCIE_EOM_VLD_REG02: 0x%08x FBNIC_PCIE_EOM_VLD_REG10: 0x%08x FBNIC_PCIE_EOM_VLD_REG11: 0x%08x FBNIC_PCIE_EOM_VLD_REG12: 0x%08x FBNIC_PCIE_EOM_VLD_MSB_REG0: 0x%08x [23:16] EOM_VLD_CNT_TOP_P_39_32: 0x%05x [15:08] EOM_VLD_CNT_MID_P_39_32: 0x%05x [07:00] EOM_VLD_CNT_BOT_P_39_32: 0x%05x FBNIC_PCIE_EOM_VLD_MSB_REG1: 0x%08x [23:16] EOM_VLD_CNT_TOP_N_39_32: 0x%05x [15:08] EOM_VLD_CNT_MID_N_39_32: 0x%05x [07:00] EOM_VLD_CNT_BOT_N_39_32: 0x%05x FBNIC_PCIE_EOM_CTRL_REG0: 0x%08x FBNIC_PCIE_DME_ENC_REG0: 0x%08x [26:26] LOCAL_FIELD_FORCE: 0x%02x [25:25] LOCAL_TX_INIT_FORCE: 0x%02x [24:24] LOCAL_TRAIN_COMP_FORCE: 0x%02x [23:23] LOCAL_ERROR_FIELD_FORCE: 0x%02x [22:22] LOCAL_STS_FIELD_FORCE: 0x%02x [21:21] LOCAL_CTRL_FIELD_FORCE: 0x%02x [07:07] LOCAL_BALANCE_CAL_EN: 0x%02x [06:06] LOCAL_ERROR_EN: 0x%02x [05:05] LOCAL_FIELD_VALID: 0x%02x [04:04] LOCAL_TX_INIT_VALID: 0x%02x [03:03] LOCAL_TRAIN_COMP_VALID: 0x%02x FBNIC_PCIE_DME_ENC_REG1: 0x%08x [31:16] LOCAL_CTRL_BITS_15_0: 0x%05x [15:00] LOCAL_STS_BITS_15_0: 0x%05x FBNIC_PCIE_DME_ENC_REG2: 0x%08x [31:16] LOCAL_CTRL_BITS_RD_15_0: 0x%05x [15:00] LOCAL_STS_BITS_RD_15_0: 0x%05x FBNIC_PCIE_DME_DEC_REG0: 0x%08x [23:23] REMOTE_RD_REQ: 0x%02x FBNIC_PCIE_DME_DEC_REG1: 0x%08x [31:16] REMOTE_CTRL_BITS_15_0: 0x%05x [15:00] REMOTE_STS_BITS_15_0: 0x%05x FBNIC_PCIE_TX_TRAIN_IF_REG0: 0x%08x [28:28] PIN_TRAIN_COMPLETE_TYPE: 0x%02x [27:27] REMOTE_STS_RECHK_EN: 0x%02x [25:25] TX_TRAIN_CHK_INIT: 0x%02x [24:24] LOCK_LOST_TIMEOUT_EN: 0x%02x [23:20] FRAME_DET_MAX_TIME_3_0: 0x%02x [16:16] LINK_TRAIN_MODE: 0x%02x [13:13] WAIT_CNT_LOCAL_ONLY: 0x%02x [10:10] TRX_TRAIN_TIMEOUT_EN: 0x%02x FBNIC_PCIE_TX_TRAIN_IF_REG1: 0x%08x [31:16] TRX_TRAIN_TMR_15_0: 0x%05x [15:00] RX_TRAIN_TMR_15_0: 0x%05x FBNIC_PCIE_TX_TRAIN_IF_REG2: 0x%08x [31:31] LOCAL_CTRL_FM_REG_EN: 0x%02x [14:13] PIN_TX_TRAIN_ERROR_1_0: 0x%02x FBNIC_PCIE_TX_TRAIN_IF_REG3: 0x%08x [08:08] REMOTE_TRAIN_COMP_RD: 0x%02x [07:07] LOCAL_TRAIN_COMP_RD: 0x%02x [06:06] TX_TRAIN_COMPLETE: 0x%02x [05:05] TX_TRAIN_FAILED: 0x%02x [04:04] RX_TRAIN_COMPLETE: 0x%02x [03:03] RX_TRAIN_FAILED: 0x%02x [02:01] TX_TRAIN_ERROR_1_0: 0x%02x [00:00] TRX_TRAIN_TIMEOUT: 0x%02x FBNIC_PCIE_TX_TRAIN_PATTTERN_REG0: 0x%08x [11:10] ETHERNET_MODE_1_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DRIVER_REG0: 0x%08x [31:31] TX_POWER_PROTECT_EN: 0x%02x [30:24] TX_POWER_MAX_6_0: 0x%05x [14:08] TX_AMP_MIN_6_0: 0x%05x [06:00] TX_AMP_MAX_6_0: 0x%05x FBNIC_PCIE_TX_TRAIN_DRIVER_REG1: 0x%08x [28:24] TX_EMPH1_MIN_4_0: 0x%02x [20:16] TX_EMPH1_MAX_4_0: 0x%02x [12:08] TX_EMPH0_MIN_4_0: 0x%02x [04:00] TX_EMPH0_MAX_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DRIVER_REG2: 0x%08x [21:21] TX_VMA_PROTECT_EN: 0x%02x [20:16] TX_VMA_MIN_4_0: 0x%02x [12:08] TX_EMPH2_MIN_4_0: 0x%02x [04:00] TX_EMPH2_MAX_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DRIVER_REG3: 0x%08x [07:04] TX_PRST_INDEX_3_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DRIVER_REG4: 0x%08x [28:24] FM_TRAIN_TX_EMPH2_4_0: 0x%02x [20:16] FM_TRAIN_TX_EMPH1_4_0: 0x%02x [12:08] FM_TRAIN_TX_EMPH0_4_0: 0x%02x [06:00] FM_TRAIN_TX_AMP_6_0: 0x%05x FBNIC_PCIE_TX_TRAIN_DEFAULT1: 0x%08x [22:16] TX_AMP_DEFAULT3_6_0: 0x%05x [14:08] TX_AMP_DEFAULT2_6_0: 0x%05x [06:00] TX_AMP_DEFAULT1_6_0: 0x%05x FBNIC_PCIE_TX_TRAIN_DEFAULT2: 0x%08x [20:16] TX_EMPH0_DEFAULT3_4_0: 0x%02x [12:08] TX_EMPH0_DEFAULT2_4_0: 0x%02x [04:00] TX_EMPH0_DEFAULT1_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DEFAULT3: 0x%08x [20:16] TX_EMPH1_DEFAULT3_4_0: 0x%02x [12:08] TX_EMPH1_DEFAULT2_4_0: 0x%02x [04:00] TX_EMPH1_DEFAULT1_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DEFAULT4: 0x%08x [20:16] TX_EMPH2_DEFAULT3_4_0: 0x%02x [12:08] TX_EMPH2_DEFAULT2_4_0: 0x%02x [04:00] TX_EMPH2_DEFAULT1_4_0: 0x%02x FBNIC_PCIE_PRBS_TRAIN0: 0x%08x [03:03] TRAIN_PRBS_CHECK_EN: 0x%02x [17:17] RX_TRAIN_COMPLETE_ISR: 0x%02x [16:16] TX_TRAIN_COMPLETE_ISR: 0x%02x [15:15] LOCAL_FIELD_DONE_ISR: 0x%02x [14:14] LOCAL_CTRL_VALID_ISR: 0x%02x [13:13] LOCAL_STS_VALID_ISR: 0x%02x [12:12] LOCAL_ERROR_VALID_ISR: 0x%02x [11:11] LOCAL_TRAIN_COMP_ISR: 0x%02x [10:10] LOCAL_TX_INIT_ISR: 0x%02x [09:09] REMOTE_TRAIN_COMP_ISR: 0x%02x [08:08] REMOTE_TX_INIT_ISR: 0x%02x [07:07] REMOTE_ERROR_VALID_ISR: 0x%02x [06:06] REMOTE_STS_VALID_ISR: 0x%02x [05:05] REMOTE_CTRL_VALID_ISR: 0x%02x [04:04] REMOTE_BALANCE_ERR_ISR: 0x%02x [03:03] DME_DEC_ERROR_ISR: 0x%02x [02:02] FRAME_DET_TIMEOUT_ISR: 0x%02x [01:01] TRX_TRAIN_TIMEOUT_ISR: 0x%02x [00:00] STS_DET_TIMEOUT_ISR: 0x%02x [17:17] RX_TRAIN_COMPLETE_MASK: 0x%02x [16:16] TX_TRAIN_COMPLETE_MASK: 0x%02x [15:15] LOCAL_FIELD_DONE_MASK: 0x%02x [14:14] LOCAL_CTRL_VALID_MASK: 0x%02x [13:13] LOCAL_STS_VALID_MASK: 0x%02x [12:12] LOCAL_ERROR_VALID_MASK: 0x%02x [11:11] LOCAL_TRAIN_COMP_MASK: 0x%02x [10:10] LOCAL_TX_INIT_MASK: 0x%02x [09:09] REMOTE_TRAIN_COMP_MASK: 0x%02x [08:08] REMOTE_TX_INIT_MASK: 0x%02x [07:07] REMOTE_ERROR_VALID_MASK: 0x%02x [06:06] REMOTE_STS_VALID_MASK: 0x%02x [05:05] REMOTE_CTRL_VALID_MASK: 0x%02x [04:04] REMOTE_BALANCE_ERR_MASK: 0x%02x [03:03] DME_DEC_ERROR_MASK: 0x%02x [02:02] FRAME_DET_TIMEOUT_MASK: 0x%02x [01:01] TRX_TRAIN_TIMEOUT_MASK: 0x%02x [00:00] STS_DET_TIMEOUT_MASK: 0x%02x FBNIC_PCIE_TRX_TRAIN_INTR: 0x%08x [17:17] RX_TRAIN_COMPLETE_ISR_CLR: 0x%02x [16:16] TX_TRAIN_COMPLETE_ISR_CLR: 0x%02x [15:15] LOCAL_FIELD_DONE_ISR_CLR: 0x%02x [14:14] LOCAL_CTRL_VALID_ISR_CLR: 0x%02x [13:13] LOCAL_STS_VALID_ISR_CLR: 0x%02x [12:12] LOCAL_ERROR_VALID_ISR_CLR: 0x%02x [11:11] LOCAL_TRAIN_COMP_ISR_CLR: 0x%02x [10:10] LOCAL_TX_INIT_ISR_CLR: 0x%02x [09:09] REMOTE_TRAIN_COMP_ISR_CLR: 0x%02x [08:08] REMOTE_TX_INIT_ISR_CLR: 0x%02x [07:07] ERROR_VALID_ISR_CLR: 0x%02x [06:06] REMOTE_STS_VALID_ISR_CLR: 0x%02x [04:04] BALANCE_ERR_ISR_CLR: 0x%02x [02:02] FRAME_DET_TIMEOUT_ISR_CLR: 0x%02x [01:01] TRX_TRAIN_TIMEOUT_ISR_CLR: 0x%02x [00:00] STS_DET_TIMEOUT_ISR_CLR: 0x%02x FBNIC_PCIE_TX_TRAIN_PAT_REG1: 0x%08x [25:16] TRAIN_PAT_NUM_RX_9_0: 0x%05x FBNIC_PCIE_TX_TRAIN_CTRL_REG1: 0x%08x [08:08] PIN_TX_TRAIN_EN_SEL: 0x%02x [07:07] TX_COE_FM_PIPE: 0x%02x FBNIC_PCIE_TX_TRAIN_DRIVER_REG5: 0x%08x [12:08] TX_EMPH3_MIN_4_0: 0x%02x [04:00] TX_EMPH3_MAX_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DRIVER_REG6: 0x%08x [04:00] FM_TRAIN_TX_EMPH3_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DEFAULT5: 0x%08x [20:16] TX_EMPH3_DEFAULT3_4_0: 0x%02x [12:08] TX_EMPH3_DEFAULT2_4_0: 0x%02x [04:00] TX_EMPH3_DEFAULT1_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_PAT_NUM1: 0x%08x [09:00] TRAIN_PAT_9_0: 0x%05x FBNIC_PCIE_TX_TRAIN_DEFAULT6: 0x%08x [30:24] TX_AMP_DEFAULT7_6_0: 0x%05x [22:16] TX_AMP_DEFAULT6_6_0: 0x%05x [14:08] TX_AMP_DEFAULT5_6_0: 0x%05x [06:00] TX_AMP_DEFAULT4_6_0: 0x%05x FBNIC_PCIE_TX_TRAIN_DEFAULT7: 0x%08x [28:24] TX_EMPH0_DEFAULT7_4_0: 0x%02x [20:16] TX_EMPH0_DEFAULT6_4_0: 0x%02x [12:08] TX_EMPH0_DEFAULT5_4_0: 0x%02x [04:00] TX_EMPH0_DEFAULT4_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DEFAULT8: 0x%08x [28:24] TX_EMPH1_DEFAULT7_4_0: 0x%02x [20:16] TX_EMPH1_DEFAULT6_4_0: 0x%02x [12:08] TX_EMPH1_DEFAULT5_4_0: 0x%02x [04:00] TX_EMPH1_DEFAULT4_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DEFAULT9: 0x%08x [28:24] TX_EMPH2_DEFAULT7_4_0: 0x%02x [20:16] TX_EMPH2_DEFAULT6_4_0: 0x%02x [12:08] TX_EMPH2_DEFAULT5_4_0: 0x%02x [04:00] TX_EMPH2_DEFAULT4_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_DEFAULT10: 0x%08x [28:24] TX_EMPH3_DEFAULT7_4_0: 0x%02x [20:16] TX_EMPH3_DEFAULT6_4_0: 0x%02x [12:08] TX_EMPH3_DEFAULT5_4_0: 0x%02x [04:00] TX_EMPH3_DEFAULT4_4_0: 0x%02x FBNIC_PCIE_TX_TRAIN_CTRL_REG4: 0x%08x [07:00] TX_TRAIN_HOLD_OFF_TMR_7_0: 0x%05x FBNIC_PCIE_PLL_RS_REG1: 0x%08x [15:00] PLL_RS_INIT_FOFFS_15_0: 0x%05x FBNIC_PCIE_PLL_RS_DTX_REG0: 0x%08x [28:28] PLL_RS_DTX_FOFFSET_SEL: 0x%02x [21:21] PLL_RS_DTX_CLAMPING_EN: 0x%02x PLL_RS_DTX_CLAMPING_TRIGGER_CLRFBNIC_PCIE_PLL_RS_REG8: 0x%08x [08:08] ANA_PLL_RS_FBCK_SEL: 0x%02x FBNIC_PCIE_PLL_RS_DTX_PHY_ALIGN_REG0FBNIC_PCIE_PLL_TS_REG1: 0x%08x [15:00] PLL_TS_INIT_FOFFS_15_0: 0x%05x FBNIC_PCIE_PLL_TS_DTX_REG0: 0x%08x [28:28] PLL_TS_DTX_FOFFSET_SEL: 0x%02x [21:21] PLL_TS_DTX_CLAMPING_EN: 0x%02x PLL_TS_DTX_CLAMPING_TRIGGER_CLRFBNIC_PCIE_PLL_TS_REG8: 0x%08x [08:08] ANA_PLL_TS_FBCK_SEL: 0x%02x FBNIC_PCIE_PLL_TS_DTX_PHY_ALIGN_REG0[27:27] CFG_USE_GEN3_PLL_CAL: 0x%02x [26:26] CFG_USE_GEN2_PLL_CAL: 0x%02x [25:25] CFG_USE_MAX_PLL_RATE: 0x%02x [24:24] CFG_SPD_CHANGE_WAIT: 0x%02x [23:23] CFG_DISABLE_TXDETVAL: 0x%02x [22:22] CFG_TXDETRX_MODE: 0x%02x [21:21] CFG_ALIGN_IDLE_HIZ: 0x%02x [20:19] CFG_GEN2_TXDATA_DLY_1_0: 0x%02x [18:17] CFG_GEN1_TXDATA_DLY_1_0: 0x%02x [16:16] CFG_TXELECIDLE_MODE: 0x%02x [15:14] CFG_FORCE_RXPRESENT_1_0: 0x%02x [13:13] CFG_FAST_SYNCH: 0x%02x [11:06] CFG_TX_ALIGN_POS_5_0: 0x%05x [04:02] PRD_TXMARGIN_2_0: 0x%02x [01:01] PRD_TXDEEMPH1: 0x%02x [00:00] PRD_TXDEEMPH0: 0x%02x [23:23] PM_ASYNC_RST_N: 0x%02x [21:21] PM_OSCCLK_AUX_CLK_EN: 0x%02x [20:20] PM_OSCCLK_PCLK_EN: 0x%02x [19:19] PM_PCLK_DPCLK_EN: 0x%02x [18:18] PM_TXDCLK_PCLK_EN: 0x%02x [17:17] PM_TX_VCMHOLD_EN: 0x%02x [15:15] PM_TXDETECTRX_EN: 0x%02x [14:14] PM_TX_IDLE_HIZ: 0x%02x [13:13] PM_TX_IDLE_LOZ: 0x%02x [11:08] PM_RX_RATE_SEL_3_0: 0x%02x [07:04] PM_TX_RATE_SEL_3_0: 0x%02x FBNIC_PCIE_LANE_CFG_STS2: 0x%08x [31:31] BEACON_DETECTED: 0x%02x [30:30] CFG_POWER_SETTLE_WAIT: 0x%02x [29:24] CFG_RXEIDETECT_DLY_5_0: 0x%05x [23:23] CFG_IVREF_MODE: 0x%02x [22:22] CFG_BEACON_MODE: 0x%02x [21:18] CFG_BEACON_TXLOZ_WAIT_3_0: 0x%02x [17:17] CFG_BEACON_RX_EN: 0x%02x [16:16] CFG_BEACON_TX_EN: 0x%02x MAC_PHY_TXDETECTRX_LOOPBACK_RD[14:14] MAC_PHY_TXELECIDLE_RD: 0x%02x [13:12] MAC_PHY_POWERDOWN_RD_1_0: 0x%02x [11:09] MAC_PHY_RATE_RD_2_0: 0x%02x [08:08] PHY_MAC_RXVALID: 0x%02x [07:07] PHY_MAC_RXELECIDLE: 0x%02x [06:06] ANA_DPHY_PLL_READY_TX: 0x%02x [05:05] MAC_PHY_RX_TERMINATION_RD: 0x%02x [04:04] ANA_DPHY_PLL_READY_RX: 0x%02x [03:03] ANA_DPHY_TXDETRX_VALID: 0x%02x [02:02] ANA_DPHY_RX_INIT_DONE: 0x%02x [01:01] ANA_DPHY_SQ_DETECTED: 0x%02x [00:00] ANA_DPHY_RXPRESENT: 0x%02x [20:16] CFG_ELB_THRESH_4_0: 0x%02x [13:13] CFG_BLK_ALIGN_CTRL_2: 0x%02x [12:11] CFG_BLK_ALIGN_CTRL_1_0: 0x%02x [08:07] CFG_GEN3_TXDATA_DLY_1_0: 0x%02x [00:00] CFG_USE_FTS_LOCK: 0x%02x [20:20] CFG_RXEI_DG_WEIGHT: 0x%02x [19:19] CFG_RXEIDET_DG_EN: 0x%02x [18:18] CFG_RX_EQ_CTRL: 0x%02x [17:17] CFG_SQ_DET_SEL: 0x%02x [16:16] CFG_RX_INIT_SEL: 0x%02x [13:13] CFG_SRIS_CTRL: 0x%02x [12:08] CFG_REF_FREF_SEL_4_0: 0x%02x [06:06] CFG_DFE_OVERRIDE: 0x%02x [05:05] CFG_DFE_UPDATE_SEL: 0x%02x [04:04] CFG_DFE_PAT_SEL: 0x%02x [03:03] CFG_DFE_EN_SEL: 0x%02x [02:00] CFG_DFE_CTRL_2_0: 0x%02x FBNIC_PCIE_LANE_CFG_STS3: 0x%08x [30:30] CFG_P1_WAKEUP: 0x%02x [29:29] CFG_P0S_IDLE_HIZ_DIS: 0x%02x [28:28] CFG_HIZ_CAL_TMR_EN: 0x%02x [27:24] CFG_HIZ_CAL_WAIT_3_0: 0x%02x [23:23] CFG_DELAY_P12_PHYST: 0x%02x [22:22] CFG_DELAY_TDR_PHYST: 0x%02x [21:16] CFG_TXCMN_DIS_DLY_5_0: 0x%05x [15:15] MAC_PHY_TXCOMPLIANCE_RD: 0x%02x [13:13] PM_REFCLK_VALID: 0x%02x [12:12] ANA_REFCLK_DIS_ACK: 0x%02x [11:11] PM_REFCLK_DIS: 0x%02x [09:09] PM_RX_TRAIN_EN: 0x%02x [08:00] PM_STS_PCLK_8_0: 0x%05x FBNIC_PCIE_DP_PIE8_CFG0: 0x%08x [17:17] PM_BEACON_RX_EN: 0x%02x [16:16] PM_BEACON_TX_EN: 0x%02x [08:08] PHY_MAC_PHYSTS: 0x%02x [30:30] CFG_PHY_RC_EP: 0x%02x [29:24] CFG_EQ_LF_5_0: 0x%05x [21:16] CFG_EQ_FS_5_0: 0x%05x [30:30] CFG_EQ_BUNDLE_DIS: 0x%02x [24:24] CFG_TX_COEFF_OVERRIDE: 0x%02x [12:12] CFG_UPDATE_POLARITY: 0x%02x [29:24] CFG_CURSOR_PRST11_5_0: 0x%05x FBNIC_PCIE_PRST_CFG16: 0x%08x [29:24] CFG_POST_CURSOR_PRST11_5_0: 0x%05x [21:16] CFG_PRE_CURSOR_PRST11_5_0: 0x%05x FBNIC_PCIE_COEFF_MAX0: 0x%08x [31:31] CFG_LINK_TRAIN_CTRL: 0x%02x [13:13] CFG_TX_SWING_EN: 0x%02x [12:12] CFG_TX_MARGIN_EN: 0x%02x FBNIC_PCIE_REMOTE_SET: 0x%08x [08:08] CFG_INVALID_REQ_SEL: 0x%02x FBNIC_PCIE_EQ_16G_CFG0: 0x%08x [14:14] CFG_PRST_INDEX_SEL: 0x%02x [13:08] CFG_EQ_16G_LF_5_0: 0x%05x [05:00] CFG_EQ_16G_FS_5_0: 0x%05x FBNIC_PCIE_EQ_32G_CFG0: 0x%08x [14:14] CFG_32G_PRST_INDEX_SEL: 0x%02x [13:08] CFG_EQ_32G_LF_5_0: 0x%05x [05:00] CFG_EQ_32G_FS_5_0: 0x%05x FBNIC_PCIE_CCIX_ESM_CTRL_STAT: 0x%08x [00:00] ESM_CAL_COMPLETE: 0x%02x FBNIC_PCIE_GLOB_RST_CLK_CTRL: 0x%08x [26:26] MODE_P3_OSC_PCLK_EN: 0x%02x [25:25] MODE_CORE_CLK_FREQ_SEL: 0x%02x [23:23] MODE_MULTICAST: 0x%02x [22:22] MODE_CORE_CLK_CTRL: 0x%02x [21:20] MODE_REFDIV_1_0: 0x%02x [19:19] MODE_PIPE_WIDTH_32: 0x%02x [18:18] MODE_MIXED_DW_DF: 0x%02x [15:08] MAIN_REVISION_7_0: 0x%05x [07:00] SUB_REVISION_7_0: 0x%05x FBNIC_PCIE_GLOB_CLK_SRC_LO: 0x%08x [31:31] CFG_USE_ASYNC_CLKREQN: 0x%02x [30:30] CFG_CLK_SRC_MASK: 0x%02x [29:29] CFG_USE_ALIGN_RDY: 0x%02x [28:28] CFG_SLOW_ALIGN: 0x%02x [27:27] CFG_FORCE_OCLK_EN: 0x%02x [25:25] CFG_USE_ALIGN_CLK: 0x%02x [24:24] BUNDLE_PLL_RDY: 0x%02x [23:21] PLL_READY_DLY_2_0: 0x%02x [20:20] BUNDLE_SAMPLE_CTRL: 0x%02x [19:16] MODE_CLK_SRC_3_0: 0x%02x [14:14] MODE_STATE_OVERRIDE: 0x%02x [13:13] MODE_RST_OVERRIDE: 0x%02x [12:12] MODE_LB_SERDES: 0x%02x [10:10] MODE_LB_SHALLOW: 0x%02x [09:09] DBG_TESTBUS_SEL_6: 0x%02x [08:08] DBG_TESTBUS_SEL_5: 0x%02x [07:07] DBG_TESTBUS_SEL_4: 0x%02x [06:03] DBG_TESTBUS_SEL_3_0: 0x%02x [02:02] MODE_MARGIN_OVERRIDE: 0x%02x [01:01] MODE_PM_OVERRIDE: 0x%02x FBNIC_PCIE_GLOB_CLK_SRC_HI: 0x%08x [28:28] PMO_POWER_VALID: 0x%02x [20:16] PULSE_LENGTH_4_0: 0x%02x [15:15] CFG_SEL_20_BITS: 0x%02x [14:14] CFG_RXTERM_EN: 0x%02x [12:12] BUNDLE_PERIOD_SEL: 0x%02x [11:11] CFG_REFCLK_VALID_POL: 0x%02x [10:09] CFG_OSC_WIN_LENGTH_1_0: 0x%02x [08:08] CFG_TURN_OFF_DIS: 0x%02x [07:07] MODE_PIPE4_IF: 0x%02x [06:05] BUNDLE_PERIOD_SCALE_1_0: 0x%02x [04:03] BIFURCATION_SEL_1_0: 0x%02x FBNIC_PCIE_GLOB_MISC_CTRL: 0x%08x [31:30] REFCLK_DISABLE_DLY_5_4: 0x%02x [29:26] REFCLK_DISABLE_DLY_3_0: 0x%02x [25:24] REFCLK_SHUTOFF_DLY_1_0: 0x%02x [23:18] REFCLK_RESTORE_DLY_5_0: 0x%05x [17:17] CLKREQ_N_OVERRIDE: 0x%02x [15:15] CFG_CLK_ACK_TMR_EN: 0x%02x [14:14] CFG_REFCLK_DET_TYPE: 0x%02x [13:13] MODE_REFCLK_DIS: 0x%02x [12:12] CFG_FREE_OSC_SEL: 0x%02x [10:08] OSC_COUNT_SCALE_2_0: 0x%02x [06:06] MODE_P1_SNOOZ: 0x%02x [05:05] CFG_RX_HIZ_SRC: 0x%02x [04:04] SQ_DETECT_OVERRIDE: 0x%02x [03:03] SQ_DETECT_SRC: 0x%02x [02:02] MODE_PCLK_CTRL: 0x%02x [01:01] MODE_P2_PHYSTS: 0x%02x [00:00] MODE_P1_CLK_REQ_N: 0x%02x FBNIC_PCIE_GLOB_DP_SAL_CFG: 0x%08x [28:24] CFG_SAL_24_20: 0x%02x [13:13] CFG_SAL_IGNORE_SQ: 0x%02x [12:12] CFG_TXELECIDLE_ASSERT: 0x%02x [09:09] CFG_SAL_FREEZE: 0x%02x [08:08] CFG_ALWAYS_ALIGN: 0x%02x [07:07] CFG_DISABLE_SKP: 0x%02x [06:06] CFG_MASK_ERRORS: 0x%02x [05:05] CFG_DISABLE_EDB: 0x%02x [04:04] CFG_NO_DISPERROR: 0x%02x [03:03] CFG_PASS_RXINFO: 0x%02x [00:00] CFG_IGNORE_PHY_RDY: 0x%02x FBNIC_PCIE_GLOB_DP_SAL_CFG1: 0x%08x [28:24] CFG_SAL_34_30: 0x%02x [20:16] CFG_SAL_14_10: 0x%02x [12:08] CFG_SAL_29_25: 0x%02x FBNIC_PCIE_GLOB_DP_SAL_CFG3: 0x%08x [26:24] CFG_SAL_45_43: 0x%02x [18:16] CFG_SAL_42_40: 0x%02x [12:08] CFG_SAL_39_35: 0x%02x [04:00] CFG_SAL_19_15: 0x%02x FBNIC_PCIE_GLOB_PROTOCOL_CFG0: 0x%08x [18:18] CFG_BUS_WIDTH_DISABLE: 0x%02x FBNIC_PCIE_GLOB_PM_CFG0: 0x%08x [15:12] CFG_PM_OSCCLK_WAIT_3_0: 0x%02x [11:08] CFG_PM_RXDEN_WAIT_3_0: 0x%02x [07:00] CFG_PM_RXDLOZ_WAIT_7_0: 0x%05x FBNIC_PCIE_GLOB_COUNTER_CTRL: 0x%08x [31:16] COUNTER_SAMPLED_15_0: 0x%05x [15:15] PMO_REFCLK_DIS: 0x%02x [13:08] COUNTER_TYPE_5_0: 0x%05x [07:07] COUNTER_SAMPLE_CLR: 0x%02x [06:06] COUNTER_SAMPLE: 0x%02x FBNIC_PCIE_GLOB_COUNTER_HI: 0x%08x [15:00] COUNTER_SAMPLED_31_16: 0x%05x FBNIC_PCIE_GLOB_PM_DP_CTRL: 0x%08x [31:30] LOW_FREQ_CNT_SCALE_1_0: 0x%02x [29:23] LOW_FREQ_PERIOD_MAX_6_0: 0x%05x [22:16] LOW_FREQ_PERIOD_MIN_6_0: 0x%05x FBNIC_PCIE_GLOB_DP_BAL_CFG0: 0x%08x [29:24] CFG_BAL_WEIGHT_35_30: 0x%05x [21:16] CFG_BAL_WEIGHT_11_6: 0x%05x [13:08] CFG_BAL_WEIGHT_29_24: 0x%05x [05:00] CFG_BAL_WEIGHT_5_0: 0x%05x FBNIC_PCIE_GLOB_DP_BAL_CFG2: 0x%08x [29:24] CFG_BAL_WEIGHT_47_42: 0x%05x [21:16] CFG_BAL_WEIGHT_23_18: 0x%05x [13:08] CFG_BAL_WEIGHT_41_36: 0x%05x [05:00] CFG_BAL_WEIGHT_17_12: 0x%05x FBNIC_PCIE_GLOB_DP_BAL_CFG4: 0x%08x [10:08] CFG_BAL_WEIGHT_53_51: 0x%02x [02:00] CFG_BAL_WEIGHT_50_48: 0x%02x FBNIC_PCIE_GLOB_BIST_CTRL: 0x%08x [26:26] BIST_RXEQTRAINING: 0x%02x [25:22] BIST_ELB_THRESH_3_0: 0x%02x [21:16] BIST_TX_ALIGN_POS_5_0: 0x%05x [15:12] BIST_TXDATAK_3_0: 0x%02x [11:11] BIST_CLK_REQ_N: 0x%02x [10:10] BIST_TXCMN_MODE_DIS: 0x%02x [09:09] BIST_RXEIDETECT_DIS: 0x%02x [08:08] BIST_RXPOLARITY: 0x%02x [07:07] BIST_TXCOMPLIANCE: 0x%02x [06:06] BIST_TXELECIDLE: 0x%02x [05:05] BIST_TXDETECTRX_LOOPBACK: 0x%02x [04:02] BIST_RATE_2_0: 0x%02x [01:00] BIST_POWERDOWN_1_0: 0x%02x FBNIC_PCIE_GLOB_BIST_TYPE: 0x%08x [29:28] BIST_SKPOS_4_3: 0x%02x [27:25] BIST_SKPOS_2_0: 0x%02x [24:24] BIST_SKPOS_SEL: 0x%02x [19:19] BIST_CONT_MONITR: 0x%02x [18:17] BIST_TYPE_1_0: 0x%02x [16:16] BIST_SELF_CHECK: 0x%02x [15:00] BIST_TXDATA_15_0: 0x%05x FBNIC_PCIE_GLOB_BIST_START: 0x%08x [31:16] BIST_WIN_LENGTH_15_0: 0x%05x [15:00] BIST_WIN_DELAY_15_0: 0x%05x FBNIC_PCIE_GLOB_BIST_MASK: 0x%08x [31:16] BIST_MASK_31_16: 0x%05x [15:00] BIST_MASK_15_0: 0x%05x FBNIC_PCIE_GLOB_BIST_RES: 0x%08x [31:16] BIST_CRC32_RES_31_16: 0x%05x [15:00] BIST_CRC32_RES_15_0: 0x%05x FBNIC_PCIE_GLOB_BIST_SEQR_CFG: 0x%08x [31:16] BIST_LFSR_SEED_15_0: 0x%05x [15:08] BIST_SEQ_N_FTS_7_0: 0x%05x [07:00] BIST_SEQ_N_DATA_7_0: 0x%05x FBNIC_PCIE_GLOB_BIST_DATA_HI: 0x%08x [15:00] BIST_TXDATA_31_16: 0x%05x FBNIC_PCIE_GLOB_BIST_LINK_EQ: 0x%08x [21:21] BIST_EQ_COMPLETE: 0x%02x [20:20] BIST_EQ_SUCCESSFUL: 0x%02x [19:16] BIST_INIT_PRST_3_0: 0x%02x [13:13] BIST_INCLD_INIT_FOM: 0x%02x [12:12] BIST_EQ_FB_MODE: 0x%02x [11:00] BIST_PRST_VECTOR_11_0: 0x%05x FBNIC_PCIE_GLOB_BIST_MARGIN: 0x%08x [26:24] MARGIN_TYPE_STAT_2_0: 0x%02x [23:16] MARGIN_PAYLOAD_STAT_7_0: 0x%05x [10:08] BIST_MARGIN_TYPE_2_0: 0x%02x [07:00] BIST_MARGIN_PAYLOAD_7_0: 0x%05x FBNIC_PCIE_GLOB_PIPE_REVISION: 0x%08x [31:16] DBG_BUS_OUT_15_0: 0x%05x [07:00] PIPE_REVISION_7_0: 0x%05x FBNIC_PCIE_GLOB_L1_SUBSTATES_CFG: 0x%08x [14:14] ASYNC_HS_BYPASS: 0x%02x [13:13] CFG_USE_SIDE_BAND: 0x%02x [12:12] MODE_PIPE4X_L1SUB: 0x%02x [03:00] P1CPM_ENC_3_0: 0x%02x FBNIC_PCIE_IN_PIN_DBG_TX_REG13: 0x%08x [17:08] PHY_GEN_TX_9_0: 0x%05x [07:07] PHY_GEN_TX_FM_REG: 0x%02x [05:05] PU_PLL_FM_REG: 0x%02x FBNIC_PCIE_IN_PIN_DBG_TX_REG14: 0x%08x [14:14] REPEAT_MODE_EN: 0x%02x [11:11] SSC_EN_FM_REG: 0x%02x [06:04] TXDCLK_NT_SEL_2_0: 0x%02x FBNIC_PCIE_IN_PIN_DBG_TX_REG15: 0x%08x [23:16] REF_FREF_SEL_TX_7_0: 0x%05x [14:14] REFCLK_SEL_TX: 0x%02x [12:12] TXDATA_GRAY_CODE_EN: 0x%02x [10:10] TXDATA_PRE_CODE_EN: 0x%02x FBNIC_PCIE_IN_PIN_DBG_RX_REG9: 0x%08x [17:08] PHY_GEN_RX_9_0: 0x%05x [07:07] PHY_GEN_RX_FM_REG: 0x%02x FBNIC_PCIE_IN_PIN_DBG_RX_REG12: 0x%08x [01:01] RX_TRAIN_EN_FM_REG: 0x%02x FBNIC_PCIE_IN_PIN_DBG_RX_REG13: 0x%08x [27:27] TX_TRAIN_EN_FM_REG: 0x%02x [23:21] RXDCLK_NT_SEL_2_0: 0x%02x [13:13] RXDCLK_25M_EN: 0x%02x [07:00] REF_FREF_SEL_RX_7_0: 0x%05x FBNIC_PCIE_IN_PIN_DBG_RX_REG14: 0x%08x [30:30] REFCLK_SEL_RX: 0x%02x FBNIC_PCIE_IN_PIN_DBG_RX_REG18: 0x%08x [30:30] RXDATA_GRAY_CODE_EN: 0x%02x [28:28] RXDATA_PRE_CODE_EN: 0x%02x FBNIC_PCIE_IN_PIN_DBG_RX_REG19: 0x%08x [25:25] DFE_UPDATE_DIS: 0x%02x FBNIC_PCIE_IN_PIN_DBG_PLL_TS_REG0: 0x%08x [06:06] ANA_PLL_TS_LOCK_RD: 0x%02x FBNIC_PCIE_IN_PIN_DBG_PLL_RS_REG0: 0x%08x [30:30] ANA_PLL_RS_LOCK_RD: 0x%02x FBNIC_PCIE_IN_PIN_DBG_PIPE_REG9: 0x%08x [10:08] MAC_PHY_RATE_2_0: 0x%02x [02:02] PHY_TXCOMPLIANCE: 0x%02x FBNIC_PCIE_IN_PIN_DBG_PIPE_REG12: 0x%08x [14:14] MAC_PHY_TXELECIDLE: 0x%02x FBNIC_PCIE_IN_PIN_DBG_PIPE_REG13: 0x%08x [06:06] PHY_RX_TERMINATION: 0x%02x [12:12] ULTRA_SHORT_TRAIN_MODE: 0x%02x FBNIC_PCIE_TRX_TRAIN_TMRS: 0x%08x [30:30] RX_TRAIN_TMR_EN: 0x%02x [29:29] TX_TRAIN_TMR_EN: 0x%02x [28:28] TX_TRAIN_FRAME_DET_TMR_EN: 0x%02x FBNIC_PCIE_DFE_CTRL_1: 0x%08x [15:08] ESM_VOLTAGE_7_0: 0x%05x FBNIC_PCIE_DFE_CTRL_3: 0x%08x [03:03] TX_TRAIN_P2P_HOLD: 0x%02x FBNIC_PCIE_DFE_CTRL_5: 0x%08x [15:15] CDRPHASE_OPT_EN: 0x%02x [14:14] SATURATE_DISABLE: 0x%02x [12:08] THRE_GOOD_4_0: 0x%02x FBNIC_PCIE_TRAIN_CTRL_2: 0x%08x [31:28] RX_RXFFE_R_INI_3_0: 0x%02x [23:23] TX_ADAPT_G0_EN: 0x%02x [22:22] TX_ADAPT_GN1_EN: 0x%02x [21:21] TX_ADAPT_G1_EN: 0x%02x [20:20] TX_ADAPT_GN2_EN: 0x%02x [26:16] ESM_PHASE_10_0: 0x%05x FBNIC_PCIE_RL2_CTRL_1: 0x%08x [07:07] CDR_MIDPOINT_EN: 0x%02x FBNIC_PCIE_TRAIN_CTRL_8: 0x%08x [17:17] TX_TRAIN_CODING_MODE: 0x%02x FBNIC_PCIE_TRAIN_PARA_1: 0x%08x [23:16] F0A_LOW_THRES_2_INIT_7_0: 0x%05x [15:08] F0A_LOW_THRES_3_INIT_7_0: 0x%05x FBNIC_PCIE_TRAIN_PARA_2: 0x%08x [06:06] GAIN_TRAIN_END_EN: 0x%02x [05:05] GAIN_TRAIN_INIT_EN: 0x%02x FBNIC_PCIE_TRAIN_SAVE_4: 0x%08x FBNIC_PCIE_TM_BUDGET_TMR_VERIFY: 0x%08x [31:24] TMR_VERIFY_TIME_B3_7_0: 0x%05x [23:16] TMR_VERIFY_TIME_B2_7_0: 0x%05x [15:08] TMR_VERIFY_TIME_B1_7_0: 0x%05x [07:00] TMR_VERIFY_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PIN_PU_PLL: 0x%08x [31:24] PIN_PU_PLL_TIME_B3_7_0: 0x%05x [23:16] PIN_PU_PLL_TIME_B2_7_0: 0x%05x [15:08] PIN_PU_PLL_TIME_B1_7_0: 0x%05x [07:00] PIN_PU_PLL_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_LOAD_INIT_TEMP_TABLEFBNIC_PCIE_TM_BUDGET_PLL_CAL_OVERALL_RATE_0FBNIC_PCIE_TM_BUDGET_PLL_CAL_CLR_0: 0x%08x [31:24] PLL_CAL_CLR_0_B3_7: 0x%05x [23:16] PLL_CAL_CLR_0_B2_7: 0x%05x [15:08] PLL_CAL_CLR_0_B1_7: 0x%05x [07:00] PLL_CAL_CLR_0_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_AMP_CAL_RATE_0[31:24] PLL_AMP_CAL_RATE_0_B3_7: 0x%05x [23:16] PLL_AMP_CAL_RATE_0_B2_7: 0x%05x [15:08] PLL_AMP_CAL_RATE_0_B1_7: 0x%05x [07:00] PLL_AMP_CAL_RATE_0_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_VDDA_CAL_RATE_0[31:24] PLL_VDDA_CAL_RATE_0_B3_7: 0x%05x [23:16] PLL_VDDA_CAL_RATE_0_B2_7: 0x%05x [15:08] PLL_VDDA_CAL_RATE_0_B1_7: 0x%05x [07:00] PLL_VDDA_CAL_RATE_0_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_CAL_FREQ_0: 0x%08x [31:24] PLL_CAL_FREQ_0_B3_7: 0x%05x [23:16] PLL_CAL_FREQ_0_B2_7: 0x%05x [15:08] PLL_CAL_FREQ_0_B1_7: 0x%05x [07:00] PLL_CAL_FREQ_0_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_DCC_CAL_RATE_0[31:24] PLL_DCC_CAL_RATE_0_B3_7: 0x%05x [23:16] PLL_DCC_CAL_RATE_0_B2_7: 0x%05x [15:08] PLL_DCC_CAL_RATE_0_B1_7: 0x%05x [07:00] PLL_DCC_CAL_RATE_0_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_LOCK_WAIT_0[31:24] PLL_LOCK_WAIT_0_B3_7: 0x%05x [23:16] PLL_LOCK_WAIT_0_B2_7: 0x%05x [15:08] PLL_LOCK_WAIT_0_B1_7: 0x%05x [07:00] PLL_LOCK_WAIT_0_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_CAL_OVERALL_RATE_1FBNIC_PCIE_TM_BUDGET_PLL_CAL_CLR_1: 0x%08x [31:24] PLL_CAL_CLR_1_B3_7_0: 0x%05x [23:16] PLL_CAL_CLR_1_B2_7_0: 0x%05x [15:08] PLL_CAL_CLR_1_B1_7_0: 0x%05x [07:00] PLL_CAL_CLR_1_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_AMP_CAL_RATE_1[31:24] PLL_AMP_CAL_RATE_1_B3_7_0: 0x%05x [23:16] PLL_AMP_CAL_RATE_1_B2_7_0: 0x%05x [15:08] PLL_AMP_CAL_RATE_1_B1_7_0: 0x%05x [07:00] PLL_AMP_CAL_RATE_1_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_VDDA_CAL_RATE_1[31:24] PLL_VDDA_CAL_RATE_1_B3_7_0: 0x%05x [23:16] PLL_VDDA_CAL_RATE_1_B2_7_0: 0x%05x [15:08] PLL_VDDA_CAL_RATE_1_B1_7_0: 0x%05x [07:00] PLL_VDDA_CAL_RATE_1_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_CAL_FREQ_1: 0x%08x [31:24] PLL_CAL_FREQ_1_B3_7_0: 0x%05x [23:16] PLL_CAL_FREQ_1_B2_7_0: 0x%05x [15:08] PLL_CAL_FREQ_1_B1_7_0: 0x%05x [07:00] PLL_CAL_FREQ_1_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_DCC_CAL_RATE_1[31:24] PLL_DCC_CAL_RATE_1_B3_7_0: 0x%05x [23:16] PLL_DCC_CAL_RATE_1_B2_7_0: 0x%05x [15:08] PLL_DCC_CAL_RATE_1_B1_7_0: 0x%05x [07:00] PLL_DCC_CAL_RATE_1_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_LOCK_WAIT_1[31:24] PLL_LOCK_WAIT_1_B3_7_0: 0x%05x [23:16] PLL_LOCK_WAIT_1_B2_7_0: 0x%05x [15:08] PLL_LOCK_WAIT_1_B1_7_0: 0x%05x [07:00] PLL_LOCK_WAIT_1_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_CAL_OVERALL_RATE_2FBNIC_PCIE_TM_BUDGET_PLL_CAL_CLR_2: 0x%08x [31:24] PLL_CAL_CLR_2_B3_7_0: 0x%05x [23:16] PLL_CAL_CLR_2_B2_7_0: 0x%05x [15:08] PLL_CAL_CLR_2_B1_7_0: 0x%05x [07:00] PLL_CAL_CLR_2_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_AMP_CAL_RATE_2[31:24] PLL_AMP_CAL_RATE_2_B3_7_0: 0x%05x [23:16] PLL_AMP_CAL_RATE_2_B2_7_0: 0x%05x [15:08] PLL_AMP_CAL_RATE_2_B1_7_0: 0x%05x [07:00] PLL_AMP_CAL_RATE_2_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_VDDA_CAL_RATE_2[31:24] PLL_VDDA_CAL_RATE_2_B3_7_0: 0x%05x [23:16] PLL_VDDA_CAL_RATE_2_B2_7_0: 0x%05x [15:08] PLL_VDDA_CAL_RATE_2_B1_7_0: 0x%05x [07:00] PLL_VDDA_CAL_RATE_2_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_CAL_FREQ_2: 0x%08x [31:24] PLL_CAL_FREQ_2_B3_7_0: 0x%05x [23:16] PLL_CAL_FREQ_2_B2_7_0: 0x%05x [15:08] PLL_CAL_FREQ_2_B1_7_0: 0x%05x [07:00] PLL_CAL_FREQ_2_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_DCC_CAL_RATE_2[31:24] PLL_DCC_CAL_RATE_2_B3_7_0: 0x%05x [23:16] PLL_DCC_CAL_RATE_2_B2_7_0: 0x%05x [15:08] PLL_DCC_CAL_RATE_2_B1_7_0: 0x%05x [07:00] PLL_DCC_CAL_RATE_2_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PLL_LOCK_WAIT_2[31:24] PLL_LOCK_WAIT_2_B3_7_0: 0x%05x [23:16] PLL_LOCK_WAIT_2_B2_7_0: 0x%05x [15:08] PLL_LOCK_WAIT_2_B1_7_0: 0x%05x [07:00] PLL_LOCK_WAIT_2_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_MASTER_REG: 0x%08x [31:24] MASTER_REG_TIME_B3_7_0: 0x%05x [23:16] MASTER_REG_TIME_B2_7_0: 0x%05x [15:08] MASTER_REG_TIME_B1_7_0: 0x%05x [07:00] MASTER_REG_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_LOAD_SPEED_TBL_GEN_5FBNIC_PCIE_TM_BUDGET_LOAD_SPEED_TBL_GEN_4FBNIC_PCIE_TM_BUDGET_LOAD_SPEED_TBL_GEN_3FBNIC_PCIE_TM_BUDGET_LOAD_SPEED_TBL_GEN_2FBNIC_PCIE_TM_BUDGET_LOAD_SPEED_TBL_GEN_1FBNIC_PCIE_TM_BUDGET_LOAD_SPEED_TBL_GEN_0LOAD_SPEED_TBL_GEN_0_TIME_B3_7LOAD_SPEED_TBL_GEN_0_TIME_B2_7LOAD_SPEED_TBL_GEN_0_TIME_B1_7LOAD_SPEED_TBL_GEN_0_TIME_B0_7FBNIC_PCIE_TM_BUDGET_TX_VDD_CAL_GEN_5FBNIC_PCIE_TM_BUDGET_TX_VDD_CAL_GEN_4FBNIC_PCIE_TM_BUDGET_TX_VDD_CAL_GEN_3FBNIC_PCIE_TM_BUDGET_TX_VDD_CAL_GEN_2FBNIC_PCIE_TM_BUDGET_TX_VDD_CAL_GEN_1FBNIC_PCIE_TM_BUDGET_TX_VDD_CAL_GEN_0[31:24] TX_VDD_CAL_GEN_0_TIME_B3_7: 0x%05x [23:16] TX_VDD_CAL_GEN_0_TIME_B2_7: 0x%05x [15:08] TX_VDD_CAL_GEN_0_TIME_B1_7: 0x%05x [07:00] TX_VDD_CAL_GEN_0_TIME_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_TX_DCC_CAL_GEN_5FBNIC_PCIE_TM_BUDGET_TX_DCC_CAL_GEN_4FBNIC_PCIE_TM_BUDGET_TX_DCC_CAL_GEN_3FBNIC_PCIE_TM_BUDGET_TX_DCC_CAL_GEN_2FBNIC_PCIE_TM_BUDGET_TX_DCC_CAL_GEN_1FBNIC_PCIE_TM_BUDGET_TX_DCC_CAL_GEN_0[31:24] TX_DCC_CAL_GEN_0_TIME_B3_7: 0x%05x [23:16] TX_DCC_CAL_GEN_0_TIME_B2_7: 0x%05x [15:08] TX_DCC_CAL_GEN_0_TIME_B1_7: 0x%05x [07:00] TX_DCC_CAL_GEN_0_TIME_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_RX_CLK_CAL_GEN_5FBNIC_PCIE_TM_BUDGET_RX_CLK_CAL_GEN_4FBNIC_PCIE_TM_BUDGET_RX_CLK_CAL_GEN_3FBNIC_PCIE_TM_BUDGET_RX_CLK_CAL_GEN_2FBNIC_PCIE_TM_BUDGET_RX_CLK_CAL_GEN_1FBNIC_PCIE_TM_BUDGET_RX_CLK_CAL_GEN_0[31:24] RX_CLK_CAL_GEN_0_TIME_B3_7: 0x%05x [23:16] RX_CLK_CAL_GEN_0_TIME_B2_7: 0x%05x [15:08] RX_CLK_CAL_GEN_0_TIME_B1_7: 0x%05x [07:00] RX_CLK_CAL_GEN_0_TIME_B0_7: 0x%05x FBNIC_PCIE_TM_BUDGET_SAMPLER_CAL: 0x%08x [31:24] SAMPLER_CAL_TIME_B3_7_0: 0x%05x [23:16] SAMPLER_CAL_TIME_B2_7_0: 0x%05x [15:08] SAMPLER_CAL_TIME_B1_7_0: 0x%05x [07:00] SAMPLER_CAL_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_SQ_CAL: 0x%08x [31:24] SQ_CAL_TIME_B3_7_0: 0x%05x [23:16] SQ_CAL_TIME_B2_7_0: 0x%05x [15:08] SQ_CAL_TIME_B1_7_0: 0x%05x [07:00] SQ_CAL_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_RX_IMP_CAL: 0x%08x [31:24] RX_IMP_CAL_TIME_B3_7_0: 0x%05x [23:16] RX_IMP_CAL_TIME_B2_7_0: 0x%05x [15:08] RX_IMP_CAL_TIME_B1_7_0: 0x%05x [07:00] RX_IMP_CAL_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_TX_IMP_CAL: 0x%08x [31:24] TX_IMP_CAL_TIME_B3_7_0: 0x%05x [23:16] TX_IMP_CAL_TIME_B2_7_0: 0x%05x [15:08] TX_IMP_CAL_TIME_B1_7_0: 0x%05x [07:00] TX_IMP_CAL_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_TOTAL_CAL_DUR: 0x%08x FBNIC_PCIE_TM_BUDGET_SPD_TO_TGT_SPEEDFBNIC_PCIE_TM_BUDGET_PIN_PU_TO_PLL_READYFBNIC_PCIE_TM_BUDGET_RX_INIT: 0x%08x [31:24] RX_INIT_TIME_B3_7_0: 0x%05x [23:16] RX_INIT_TIME_B2_7_0: 0x%05x [15:08] RX_INIT_TIME_B1_7_0: 0x%05x [07:00] RX_INIT_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_SPD_TO_PLL_READY_RX_TXFBNIC_PCIE_TM_BUDGET_P0_TO_P1_TRANS: 0x%08x [31:24] PCIE_P0_TO_P1_TIME_B3_7_0: 0x%05x [23:16] PCIE_P0_TO_P1_TIME_B2_7_0: 0x%05x [15:08] PCIE_P0_TO_P1_TIME_B1_7_0: 0x%05x [07:00] PCIE_P0_TO_P1_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_P2_TRANS: 0x%08x [31:24] PCIE_P2_TIME_B3_7_0: 0x%05x [23:16] PCIE_P2_TIME_B2_7_0: 0x%05x [15:08] PCIE_P2_TIME_B1_7_0: 0x%05x [07:00] PCIE_P2_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_P2_TO_P1_TRANS: 0x%08x [31:24] PCIE_P2_TO_P1_TIME_B3_7_0: 0x%05x [23:16] PCIE_P2_TO_P1_TIME_B2_7_0: 0x%05x [15:08] PCIE_P2_TO_P1_TIME_B1_7_0: 0x%05x [07:00] PCIE_P2_TO_P1_TIME_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_P1_TO_P0_TRANS: 0x%08x [31:24] PCIE_P1_TO_P0_TIME_B3_7_0: 0x%05x [23:16] PCIE_P1_TO_P0_TIME_B2_7_0: 0x%05x [15:08] PCIE_P1_TO_P0_TIME_B1_7_0: 0x%05x [07:00] PCIE_P1_TO_P0_TIME_B0_7_0: 0x%05x FBNIC_PCIE_SELLV_VREF_CAL_1: 0x%08x [31:16] POWER_UP_TEMP_15_0: 0x%05x FBNIC_PCIE_SELLV_VREF_CAL_2: 0x%08x [31:24] CH0_POWER_UP_VAL_7_0: 0x%05x [23:16] CH1_POWER_UP_VAL_7_0: 0x%05x [15:08] CH2_POWER_UP_VAL_7_0: 0x%05x [07:00] CH3_POWER_UP_VAL_7_0: 0x%05x FBNIC_PCIE_VREF_VDDACAL: 0x%08x [31:24] VREF_VDDACAL_VAL_7_0: 0x%05x [23:16] VREF_VDDACAL_EN_7_0: 0x%05x [15:08] POWER_ON_NCAL_LN_7_0: 0x%05x [07:00] POWER_ON_PCAL_LN_7_0: 0x%05x FBNIC_PCIE_VTH_TXIMPCAL_NPMOS_OVERRIDEVTH_TXIMPCAL_PMOS_OVERRIDE_VAL_7_0VTH_TXIMPCAL_NMOS_OVERRIDE_VAL_7_0VTH_TXIMPCAL_NPMOS_OVERRIDE_EN_7_0FBNIC_PCIE_PLL_TEMPC_STRESS_MIN_MAX_VCONPLL_TEMPC_STRESS_MAX_VCON_15_0PLL_TEMPC_STRESS_MIN_VCON_15_0FBNIC_PCIE_PLL_TEMPC_STRESS_BST: 0x%08x FBNIC_PCIE_PLL_TEMPC_STRESS_CONT_CAL_ENPLL_TEMPC_STRESS_CONT_CAL_EN_7_0FBNIC_PCIE_CMN_REG_91: 0x%08x [07:04] VTH_RXIMPCAL_3_0: 0x%02x FBNIC_PCIE_CMN_REG_103: 0x%08x [05:03] VTH_TXIMPCAL_2_0: 0x%02x FBNIC_PCIE_MCU_CTRL_0: 0x%08x [09:09] INIT_XDATA_FROM_PMEM: 0x%02x [08:08] INIT_DONE_CMN: 0x%02x [07:07] MCU_INIT_DONE: 0x%02x FBNIC_PCIE_MEM_CTRL_4: 0x%08x [28:28] IRAM_ECC_2ERR_SET_CMN: 0x%02x [27:27] CACHE_ECC_2ERR_SET_CMN: 0x%02x [26:26] XDATA_ECC_2ERR_SET_CMN: 0x%02x [25:25] IRAM_ECC_1ERR_SET_CMN: 0x%02x [24:24] CACHE_ECC_1ERR_SET_CMN: 0x%02x [23:23] XDATA_ECC_1ERR_SET_CMN: 0x%02x [22:22] IRAM_ECC_2ERR_CLR_CMN: 0x%02x [21:21] CACHE_ECC_2ERR_CLR_CMN: 0x%02x [20:20] XDATA_ECC_2ERR_CLR_CMN: 0x%02x [19:19] IRAM_ECC_1ERR_CLR_CMN: 0x%02x [18:18] CACHE_ECC_1ERR_CLR_CMN: 0x%02x [17:17] XDATA_ECC_1ERR_CLR_CMN: 0x%02x [16:16] IRAM_ECC_2ERR_EN_CMN: 0x%02x [15:15] CACHE_ECC_2ERR_EN_CMN: 0x%02x [14:14] XDATA_ECC_2ERR_EN_CMN: 0x%02x [13:13] IRAM_ECC_1ERR_EN_CMN: 0x%02x [12:12] CACHE_ECC_1ERR_EN_CMN: 0x%02x [11:11] XDATA_ECC_1ERR_EN_CMN: 0x%02x [10:10] IRAM_ECC_2ERR_CMN: 0x%02x [09:09] CACHE_ECC_2ERR_CMN: 0x%02x [08:08] XDATA_ECC_2ERR_CMN: 0x%02x [07:07] IRAM_ECC_1ERR_CMN: 0x%02x [06:06] CACHE_ECC_1ERR_CMN: 0x%02x [05:05] XDATA_ECC_1ERR_CMN: 0x%02x FBNIC_PCIE_MEM_CMN_ECC_ERR_ADDR0: 0x%08x [31:24] CACHE_ECC_ERR_ADDR_CMN_7_0: 0x%05x [23:16] IRAM_ECC_ERR_ADDR_CMN_7_0: 0x%05x [08:00] XDATA_ECC_ERR_ADDR_CMN_8_0: 0x%05x [15:00] DIG_INT_RSVD0_15_0: 0x%05x [29:24] TESTBUS_SEL_LO0_CMN_5_0: 0x%05x [31:28] TESTBUS_SEL0_3_0: 0x%02x [13:13] TESTBUS_HI8BSEL_8BMODE: 0x%02x [15:00] DIG_TEST_BUS_15_0: 0x%05x [13:08] TESTBUS_SEL_HI0_CMN_5_0: 0x%05x [23:23] PHY_ISOLATE_MODE: 0x%02x [21:21] SFT_RST_NO_REG_CMN: 0x%02x [20:20] SFT_RST_ONLY_REG: 0x%02x FBNIC_PCIE_PM_CMN_REG1: 0x%08x [27:26] BEACON_DIVIDER_1_0: 0x%02x FBNIC_PCIE_IN_CMN_PIN_REG2: 0x%08x FBNIC_PCIE_PROCMON_REG1: 0x%08x [07:04] ANA_PROC_VAL_3_0: 0x%02x FBNIC_PCIE_CLKGEN_CMN_REG1: 0x%08x [01:01] PHY_MCU_REMOTE_ACK: 0x%02x [00:00] PHY_MCU_REMOTE_REQ: 0x%02x [01:01] FAST_POWER_ON_EN: 0x%02x FBNIC_PCIE_XDATA_MEM_CSUM_CMN_0: 0x%08x FBNIC_PCIE_XDATA_MEM_CSUM_CMN_1: 0x%08x FBNIC_PCIE_XDATA_MEM_CSUM_CMN_2: 0x%08x [01:01] XDATA_MEM_CSUM_PASS_CMN: 0x%02x [00:00] XDATA_MEM_CSUM_RST_CMN: 0x%02x FBNIC_PCIE_IN_PIN_DBG_CMN_REG8: 0x%08x [23:23] BG_RDY_FM_REG: 0x%02x [15:00] MCU_FREQ_15_0: 0x%05x FBNIC_PCIE_IN_PIN_DBG_CMN_REG9: 0x%08x [11:11] PHY_MODE_FM_REG: 0x%02x FBNIC_PCIE_IN_PIN_DBG_CMN_REG10: 0x%08x FBNIC_PCIE_FW_VERSION: 0x%08x [31:24] FW_MAJ_VER_7_0: 0x%05x [23:16] FW_MIN_VER_7_0: 0x%05x [15:08] FW_PATCH_VER_7_0: 0x%05x [07:00] FW_BUILD_VER_7_0: 0x%05x FBNIC_PCIE_CTRL_CONF0: 0x%08x [29:29] APTA_TRAIN_SIM_EN: 0x%02x [23:23] BYPASS_SPEED_TABLE_LOAD: 0x%02x [22:22] BYPASS_XDAT_INIT: 0x%02x [21:21] BYPASS_POWER_ON_DELAY: 0x%02x [20:18] BYPASS_DELAY_2_0: 0x%02x [17:17] POWER_UP_SIMPLE_EN: 0x%02x [15:15] LATENCY_REDUCE_EN: 0x%02x [14:14] TRAIN_SIM_CODE_SEL: 0x%02x [11:11] EXT_FORCE_CAL_DONE: 0x%02x [04:04] ANA_CLK100M_125M_SEL: 0x%02x [03:03] ANA_CLK100M_125M_EN: 0x%02x FBNIC_PCIE_CTRL_CONF7: 0x%08x [31:24] CAL_SQ_THRESH_IN_7_0: 0x%05x FBNIC_PCIE_TRAIN_IF_CONF: 0x%08x FBNIC_PCIE_CTRL_CONF8: 0x%08x [16:16] AUTO_RX_INIT_EN: 0x%02x [07:00] MASTER_MCU_SEL_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH1: 0x%08x [31:24] CAL_PROC_TT2FF_RING2_7_0: 0x%05x [23:16] CAL_PROC_SUBSS_RING1_7_0: 0x%05x [15:08] CAL_PROC_SS2TT_RING1_7_0: 0x%05x [07:00] CAL_PROC_TT2FF_RING1_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH2: 0x%08x [31:24] CAL_PROC_SS2TT_RING3_7_0: 0x%05x [23:16] CAL_PROC_TT2FF_RING3_7_0: 0x%05x [15:08] CAL_PROC_SUBSS_RING2_7_0: 0x%05x [07:00] CAL_PROC_SS2TT_RING2_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH3: 0x%08x [31:24] CAL_PROC_SUBSS_RING4_7_0: 0x%05x [23:16] CAL_PROC_SS2TT_RING4_7_0: 0x%05x [15:08] CAL_PROC_TT2FF_RING4_7_0: 0x%05x [07:00] CAL_PROC_SUBSS_RING3_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH4: 0x%08x [31:24] CAL_PROC_TT2FF_RING6_7_0: 0x%05x [23:16] CAL_PROC_SUBSS_RING5_7_0: 0x%05x [15:08] CAL_PROC_SS2TT_RING5_7_0: 0x%05x [07:00] CAL_PROC_TT2FF_RING5_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH5: 0x%08x [31:24] CAL_PROC_SS2TT_RING7_7_0: 0x%05x [23:16] CAL_PROC_TT2FF_RING7_7_0: 0x%05x [15:08] CAL_PROC_SUBSS_RING6_7_0: 0x%05x [07:00] CAL_PROC_SS2TT_RING6_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH6: 0x%08x [31:24] CAL_PROC_SUBSS_RING8_7_0: 0x%05x [23:16] CAL_PROC_SS2TT_RING8_7_0: 0x%05x [15:08] CAL_PROC_TT2FF_RING8_7_0: 0x%05x [07:00] CAL_PROC_SUBSS_RING7_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH7: 0x%08x [31:24] CAL_PROC_TT2FF_RING10_7_0: 0x%05x [23:16] CAL_PROC_SUBSS_RING9_7_0: 0x%05x [15:08] CAL_PROC_SS2TT_RING9_7_0: 0x%05x [07:00] CAL_PROC_TT2FF_RING9_7_0: 0x%05x FBNIC_PCIE_PROC_THRESH8: 0x%08x [15:08] CAL_PROC_SUBSS_RING10_7_0: 0x%05x [07:00] CAL_PROC_SS2TT_RING10_7_0: 0x%05x FBNIC_PCIE_COMMON_CONF_UPDATE_NEEDEDCOMMON_CONF_UPDATE_NEEDED_LN0_7_0COMMON_CONF_UPDATE_NEEDED_LN1_7_0COMMON_CONF_UPDATE_NEEDED_LN2_7_0COMMON_CONF_UPDATE_NEEDED_LN3_7_0FBNIC_PCIE_COMMON_CONF_UPDATE_DONE: 0x%08x [31:24] REG_MAJ_VOTE_DONE_7_0: 0x%05x FBNIC_PCIE_MCU_SOFT_RST_OCCURRED: 0x%08x FBNIC_PCIE_REFCLK_DIS_FALLING_RESP: 0x%08x REFCLK_DIS_FALLING_RESP_LN0_7_0REFCLK_DIS_FALLING_RESP_LN1_7_0REFCLK_DIS_FALLING_RESP_LN2_7_0REFCLK_DIS_FALLING_RESP_LN3_7_0FBNIC_PCIE_REFCLK_DIS_FALLING_QUERY: 0x%08x [23:16] ANA_PU_SQ_7_0: 0x%05x FBNIC_PCIE_PLL_DBG_MODE: 0x%08x [31:24] PLL_DBG_MODE_7_0: 0x%05x TXVCO_SF_ICPTAT_SEL_DBG_VAL_7_0PLL_RS_VCOAMP_VTH_SEL_DBG_VAL_7_0[07:00] LOOKUP_TABLE_BYPASS_7_0: 0x%05x FBNIC_PCIE_MASTER_REG_CAL_RES: 0x%08x [31:24] MASTER_REG_CAL_RES_LN0_7_0: 0x%05x [23:16] MASTER_REG_CAL_RES_LN1_7_0: 0x%05x [15:08] MASTER_REG_CAL_RES_LN2_7_0: 0x%05x [07:00] MASTER_REG_CAL_RES_LN3_7_0: 0x%05x FBNIC_PCIE_MASTER_REG_CAL_SYNC: 0x%08x [25:25] MASTER_REG_CAL_DONE_LN3: 0x%02x [24:24] MASTER_REG_CAL_REQ_LN3: 0x%02x [17:17] MASTER_REG_CAL_DONE_LN2: 0x%02x [16:16] MASTER_REG_CAL_REQ_LN2: 0x%02x [09:09] MASTER_REG_CAL_DONE_LN1: 0x%02x [08:08] MASTER_REG_CAL_REQ_LN1: 0x%02x [01:01] MASTER_REG_CAL_DONE_LN0: 0x%02x [00:00] MASTER_REG_CAL_REQ_LN0: 0x%02x FBNIC_PCIE_SELLV_RX_A90_DATACLK_OVERRIDESELLV_RX_A90_DATACLK_OVERRIDE_EN_7_0SELLV_RX_A90_DATACLK_OVERRIDE_VAL_7_0FBNIC_PCIE_TM_BUDGET_TMR_VERIFY_CMN: 0x%08x [31:24] TMR_VERIFY_TIME_B3_CMN_7_0: 0x%05x [23:16] TMR_VERIFY_TIME_B2_CMN_7_0: 0x%05x [15:08] TMR_VERIFY_TIME_B1_CMN_7_0: 0x%05x [07:00] TMR_VERIFY_TIME_B0_CMN_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_CMN_DET_PIN_PIL[31:24] CMN_DET_PIN_PU_PLL_B3_7_0: 0x%05x [23:16] CMN_DET_PIN_PU_PLL_B2_7_0: 0x%05x [15:08] CMN_DET_PIN_PU_PLL_B1_7_0: 0x%05x [07:00] CMN_DET_PIN_PU_PLL_B0_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_TSEN_ON_IN: 0x%08x [31:24] TSEN_ON_TIME_B3_CMN_7_0: 0x%05x [23:16] TSEN_ON_TIME_B2_CMN_7_0: 0x%05x [15:08] TSEN_ON_TIME_B1_CMN_7_0: 0x%05x [07:00] TSEN_ON_TIME_B0_CMN_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_PROC_CAL_IN: 0x%08x [31:24] PROC_CAL_TIME_B3_CMN_7_0: 0x%05x [23:16] PROC_CAL_TIME_B2_CMN_7_0: 0x%05x [15:08] PROC_CAL_TIME_B1_CMN_7_0: 0x%05x [07:00] PROC_CAL_TIME_B0_CMN_7_0: 0x%05x FBNIC_PCIE_TM_BUDGET_ALL_TOTAL_CAL_DURFBNIC_PCIE_DYN_PLL_RATE_LNS_0_1: 0x%08x [31:24] DYN_PLL_RATE_RX_LN0_7_0: 0x%05x [23:16] DYN_PLL_RATE_TX_LN0_7_0: 0x%05x [15:08] DYN_PLL_RATE_RX_LN1_7_0: 0x%05x [07:00] DYN_PLL_RATE_TX_LN1_7_0: 0x%05x FBNIC_PCIE_DYN_PLL_RATE_2_3: 0x%08x [31:24] DYN_PLL_RATE_RX_LN2_7_0: 0x%05x [23:16] DYN_PLL_RATE_TX_LN2_7_0: 0x%05x [15:08] DYN_PLL_RATE_RX_LN3_7_0: 0x%05x [07:00] DYN_PLL_RATE_TX_LN3_7_0: 0x%05x FBNIC_PCIE_DYN_PLL_REQ: 0x%08x [31:24] DYN_PLL_SEL_REQ_LN0_7_0: 0x%05x [23:16] DYN_PLL_SEL_REQ_LN1_7_0: 0x%05x [15:08] DYN_PLL_SEL_REQ_LN2_7_0: 0x%05x [07:00] DYN_PLL_SEL_REQ_LN3_7_0: 0x%05x FBNIC_PCIE_DYN_PLL_MSG: 0x%08x [31:24] DYN_PLL_SEL_MSG_LN0_7_0: 0x%05x [23:16] DYN_PLL_SEL_MSG_LN1_7_0: 0x%05x [15:08] DYN_PLL_SEL_MSG_LN2_7_0: 0x%05x [07:00] DYN_PLL_SEL_MSG_LN3_7_0: 0x%05x FBNIC_PCIE_DYN_PLL_ACT: 0x%08x [31:24] DYN_PLL_ACT_LN0_7_0: 0x%05x [23:16] DYN_PLL_ACT_LN1_7_0: 0x%05x [15:08] DYN_PLL_ACT_LN2_7_0: 0x%05x [07:00] DYN_PLL_ACT_LN3_7_0: 0x%05x FBNIC_PCIE_DYN_PLL_STATE: 0x%08x [31:24] DYN_PLL_RS_STATE_7_0: 0x%05x [23:16] DYN_PLL_TS_STATE_7_0: 0x%05x [15:08] DYN_PLL_EN_7_0: 0x%05x FBNIC_PCIE_DYN_PLL_SEQ: 0x%08x [31:24] DYN_PLL_SEQ_LN0_7_0: 0x%05x [23:16] DYN_PLL_SEQ_LN1_7_0: 0x%05x [15:08] DYN_PLL_SEQ_LN2_7_0: 0x%05x [07:00] DYN_PLL_SEQ_LN3_7_0: 0x%05x FBNIC_PCIE_AP_ARG_CMN: 0x%08x [23:16] AP_MODE_CMN_7_0: 0x%05x [15:00] AP_ARG_CMN_15_0: 0x%05x FBNIC_PCIE_DYN_PLL_SEQ_INTERN: 0x%08x [31:24] DYN_PLL_SEQ_INTERN_LN0_7_0: 0x%05x [23:16] DYN_PLL_SEQ_INTERN_LN1_7_0: 0x%05x [15:08] DYN_PLL_SEQ_INTERN_LN2_7_0: 0x%05x [07:00] DYN_PLL_SEQ_INTERN_LN3_7_0: 0x%05x FBNIC_PCIE_DYN_PLL_RATE_INTERN_LNS_0_1DYN_PLL_RATE_RX_INTERN_LN0_7_0DYN_PLL_RATE_TX_INTERN_LN0_7_0DYN_PLL_RATE_RX_INTERN_LN1_7_0DYN_PLL_RATE_TX_INTERN_LN1_7_0FBNIC_PCIE_DYN_PLL_RATE_INTERN_LNS_2_3DYN_PLL_RATE_RX_INTERN_LN2_7_0DYN_PLL_RATE_TX_INTERN_LN2_7_0DYN_PLL_RATE_RX_INTERN_LN3_7_0DYN_PLL_RATE_TX_INTERN_LN3_7_0length failed FBNIC_CSR_END_CMS_QSPI [03:03] PU_LB: 0x%02x [04:04] RXCLK_2X_SEL: 0x%02x [02:02] TXCLK_2X_SEL: 0x%02x [20:20] PLL_READY_TX: 0x%02x [18:18] TX_IDLE: 0x%02x [30:30] TXD_INV: 0x%02x [31:31] TX_SEL_BITS: 0x%02x [23:17] SSC_AMP_6_0: 0x%05x [15:08] CNT_INI_7_0: 0x%05x [30:30] TX_PAM2_EN: 0x%02x FBNIC_PCIE_DTX_REG2: 0x%08x [04:04] LN_ALIGN_OFF: 0x%02x [03:03] MASTER_EN: 0x%02x FBNIC_PCIE_MON_TOP: 0x%08x [31:31] PT_TX_EN: 0x%02x [05:05] PT_TX_RST: 0x%02x [22:22] PCIE_MODE: 0x%02x [24:24] PLL_READY_RX: 0x%02x [19:19] RX_INIT_DONE: 0x%02x FBNIC_PCIE_RX_SYS: 0x%08x [31:31] RX_SEL_BITS: 0x%02x [00:00] RX_PAM2_EN: 0x%02x [06:06] FRAME_FOUND: 0x%02x [30:30] DET_BYPASS: 0x%02x [29:29] RXD_INV: 0x%02x FBNIC_PCIE_DTL_REG0: 0x%08x [14:14] DTL_FLOOP_EN: 0x%02x FBNIC_PCIE_DTL_REG2: 0x%08x FBNIC_PCIE_SQ_REG0: 0x%08x [31:16] SQ_LPF_15_0: 0x%05x [12:12] SQ_LPF_EN: 0x%02x [23:23] PT_RX_EN: 0x%02x [08:08] PT_TRX_EN: 0x%02x [07:07] PT_RX_RST: 0x%02x [01:01] PT_RX_PASS: 0x%02x [00:00] PT_RX_LOCK: 0x%02x [29:29] SYNC_POL: 0x%02x [05:05] SYNC_FOUND: 0x%02x FBNIC_PCIE_MCU_CTRL: 0x%08x [26:26] ECC_EN: 0x%02x [07:00] MCU_ID_7_0: 0x%05x FBNIC_PCIE_SYS0: 0x%08x [06:06] INIT_DONE: 0x%02x [29:29] DFE_SQ_EN: 0x%02x [08:08] EOM_CNT_CLR: 0x%02x [17:17] DME_ENC_EN: 0x%02x [08:08] LOCAL_RD_REQ: 0x%02x TX_TRAIN_MAX_TMR_FRAME_LOCKTX_TRAIN_START_WAIT_TIME_1_0[12:11] %s: 0x%02x FBNIC_PCIE_INTR_REG0: 0x%08x FBNIC_PCIE_INTR_REG1: 0x%08x PLL_RS_DTX_CLAMPING_TRIGGER[22:22] %s: 0x%02x PLL_RS_DTX_CLAMPING_SEL_1_0[19:18] %s: 0x%02x [22:22] TXFOFFS_EN: 0x%02x PLL_TS_DTX_CLAMPING_TRIGGERPLL_TS_DTX_CLAMPING_SEL_1_0FBNIC_PCIE_LANE_CFG0: 0x%08x [05:05] PRD_TXSWING: 0x%02x FBNIC_PCIE_LANE_STS0: 0x%08x [31:26] PM_STATE_5_0: 0x%05x [25:25] PM_CLK_REQ_N: 0x%02x [24:24] PM_PIPE_64B: 0x%02x [22:22] PM_DP_RST_N: 0x%02x [16:16] PM_PU_IVREF: 0x%02x [12:12] PM_RX_INIT: 0x%02x [03:03] PM_PU_RX: 0x%02x [02:02] PM_PU_TX: 0x%02x [01:01] PM_PU_PLL: 0x%02x [00:00] PM_RST: 0x%02x FBNIC_PCIE_LANE_CFG2: 0x%08x CFG_GEN3_TXELECIDLE_DLY_1_0[06:05] %s: 0x%02x FBNIC_PCIE_LANE_CFG4: 0x%08x [07:07] CFG_SSC_CTRL: 0x%02x [14:14] PM_RX_HIZ: 0x%02x [10:10] PM_PU_SQ: 0x%02x [26:26] MODE_PIE8_EQ: 0x%02x [24:24] MODE_PIE8_IF: 0x%02x FBNIC_PCIE_EQ_CFG0: 0x%08x FBNIC_PCIE_EQ_CFG1: 0x%08x FBNIC_PCIE_PRST_CFG4: 0x%08x [01:01] ESM_CAL_REQ: 0x%02x [24:24] PHY_RST: 0x%02x [17:17] REG_RST: 0x%02x [16:16] PIPE_SFT_RST: 0x%02x [26:26] MODE_P2_OFF: 0x%02x [11:11] MODE_LB_DEEP: 0x%02x [00:00] MODE_BIST: 0x%02x [31:31] PULSE_DONE: 0x%02x [24:24] CFG_UPDATE: 0x%02x [02:02] LN_MASTER: 0x%02x [01:01] LN_BREAK: 0x%02x [00:00] LN_START: 0x%02x [16:16] CLKREQ_N_SRC: 0x%02x [11:11] RCB_RXEN_SRC: 0x%02x [07:07] MODE_P1_OFF: 0x%02x [20:16] CFG_SAL_4_0: 0x%02x CFG_GEN2_TXELECIDLE_DLY_1_0[11:10] %s: 0x%02x CFG_GEN1_TXELECIDLE_DLY_1_0[02:01] %s: 0x%02x [04:00] CFG_SAL_9_5: 0x%02x CFG_PIPE_MSG_BUS_PROTOCOL_SEL[14:14] PMO_PU_SQ: 0x%02x [31:31] BIST_START: 0x%02x [30:30] BIST_UPDATE: 0x%02x [31:31] BIST_DONE: 0x%02x [30:30] BIST_PASS: 0x%02x [23:23] BIST_PAT_SEL: 0x%02x [15:15] REMOVAL_CTRL: 0x%02x [11:08] P1_2_ENC_3_0: 0x%02x [07:04] P1_1_ENC_3_0: 0x%02x [06:06] PU_PLL: 0x%02x [04:04] PU_TX: 0x%02x [03:03] PU_TX_FM_REG: 0x%02x [12:12] SSC_EN: 0x%02x [02:02] TXDCLK_NT_EN: 0x%02x [00:00] TXDCLK_4X_EN: 0x%02x [06:06] PU_RX: 0x%02x [04:04] RX_INIT: 0x%02x [02:02] RX_TRAIN_EN: 0x%02x [30:30] SYNC_DET_EN: 0x%02x [28:28] TX_TRAIN_EN: 0x%02x [19:19] RXDCLK_NT_EN: 0x%02x [17:17] RXDCLK_4X_EN: 0x%02x [29:29] DFE_EN: 0x%02x [27:27] DFE_PAT_DIS: 0x%02x [16:16] LOOPBACK: 0x%02x FBNIC_PCIE_CAL_CTRL1: 0x%08x [26:26] TX_CAL_DONE: 0x%02x [25:25] RX_CAL_DONE: 0x%02x FBNIC_PCIE_CAL_CTRL3: 0x%08x [04:04] EOM_DFE_CALL: 0x%02x [03:03] EOM_READY: 0x%02x [02:02] TX_NO_INIT: 0x%02x [01:01] RX_NO_INIT: 0x%02x [18:18] ESM_EN: 0x%02x FBNIC_PCIE_ESM_REG0: 0x%08x RES_F0A_HIGH_THRES_INIT_7_0[07:00] %s: 0x%05x TX_TRAIN_START_DELAY_TIME_1_0[15:14] %s: 0x%02x TX_TRAIN_START_DELAY_TIME_EN[31:24] B3_7_0: 0x%05x [23:16] B2_7_0: 0x%05x [15:08] B1_7_0: 0x%05x [07:00] B0_7_0: 0x%05x PLL_CAL_OVERALL_RATE_0_B3_7[31:24] %s: 0x%05x PLL_CAL_OVERALL_RATE_0_B2_7[23:16] %s: 0x%05x PLL_CAL_OVERALL_RATE_0_B1_7[15:08] %s: 0x%05x PLL_CAL_OVERALL_RATE_0_B0_7PLL_CAL_OVERALL_RATE_1_B3_7_0PLL_CAL_OVERALL_RATE_1_B2_7_0PLL_CAL_OVERALL_RATE_1_B1_7_0PLL_CAL_OVERALL_RATE_1_B0_7_0PLL_CAL_OVERALL_RATE_2_B3_7_0PLL_CAL_OVERALL_RATE_2_B2_7_0PLL_CAL_OVERALL_RATE_2_B1_7_0PLL_CAL_OVERALL_RATE_2_B0_7_0TX_VDD_CAL_GEN_5_TIME_B3_7_0TX_VDD_CAL_GEN_5_TIME_B2_7_0TX_VDD_CAL_GEN_5_TIME_B1_7_0TX_VDD_CAL_GEN_5_TIME_B0_7_0TX_VDD_CAL_GEN_4_TIME_B3_7_0TX_VDD_CAL_GEN_4_TIME_B2_7_0TX_VDD_CAL_GEN_4_TIME_B1_7_0TX_VDD_CAL_GEN_4_TIME_B0_7_0TX_VDD_CAL_GEN_3_TIME_B3_7_0TX_VDD_CAL_GEN_3_TIME_B2_7_0TX_VDD_CAL_GEN_3_TIME_B1_7_0TX_VDD_CAL_GEN_3_TIME_B0_7_0TX_VDD_CAL_GEN_2_TIME_B3_7_0TX_VDD_CAL_GEN_2_TIME_B2_7_0TX_VDD_CAL_GEN_2_TIME_B1_7_0TX_VDD_CAL_GEN_2_TIME_B0_7_0TX_VDD_CAL_GEN_1_TIME_B3_7_0TX_VDD_CAL_GEN_1_TIME_B2_7_0TX_VDD_CAL_GEN_1_TIME_B1_7_0TX_VDD_CAL_GEN_1_TIME_B0_7_0TX_DCC_CAL_GEN_5_TIME_B3_7_0TX_DCC_CAL_GEN_5_TIME_B2_7_0TX_DCC_CAL_GEN_5_TIME_B1_7_0TX_DCC_CAL_GEN_5_TIME_B0_7_0TX_DCC_CAL_GEN_4_TIME_B3_7_0TX_DCC_CAL_GEN_4_TIME_B2_7_0TX_DCC_CAL_GEN_4_TIME_B1_7_0TX_DCC_CAL_GEN_4_TIME_B0_7_0TX_DCC_CAL_GEN_3_TIME_B3_7_0TX_DCC_CAL_GEN_3_TIME_B2_7_0TX_DCC_CAL_GEN_3_TIME_B1_7_0TX_DCC_CAL_GEN_3_TIME_B0_7_0TX_DCC_CAL_GEN_2_TIME_B3_7_0TX_DCC_CAL_GEN_2_TIME_B2_7_0TX_DCC_CAL_GEN_2_TIME_B1_7_0TX_DCC_CAL_GEN_2_TIME_B0_7_0TX_DCC_CAL_GEN_1_TIME_B3_7_0TX_DCC_CAL_GEN_1_TIME_B2_7_0TX_DCC_CAL_GEN_1_TIME_B1_7_0TX_DCC_CAL_GEN_1_TIME_B0_7_0RX_CLK_CAL_GEN_5_TIME_B3_7_0RX_CLK_CAL_GEN_5_TIME_B2_7_0RX_CLK_CAL_GEN_5_TIME_B1_7_0RX_CLK_CAL_GEN_5_TIME_B0_7_0RX_CLK_CAL_GEN_4_TIME_B3_7_0RX_CLK_CAL_GEN_4_TIME_B2_7_0RX_CLK_CAL_GEN_4_TIME_B1_7_0RX_CLK_CAL_GEN_4_TIME_B0_7_0RX_CLK_CAL_GEN_3_TIME_B3_7_0RX_CLK_CAL_GEN_3_TIME_B2_7_0RX_CLK_CAL_GEN_3_TIME_B1_7_0RX_CLK_CAL_GEN_3_TIME_B0_7_0RX_CLK_CAL_GEN_2_TIME_B3_7_0RX_CLK_CAL_GEN_2_TIME_B2_7_0RX_CLK_CAL_GEN_2_TIME_B1_7_0RX_CLK_CAL_GEN_2_TIME_B0_7_0RX_CLK_CAL_GEN_1_TIME_B3_7_0RX_CLK_CAL_GEN_1_TIME_B2_7_0RX_CLK_CAL_GEN_1_TIME_B1_7_0RX_CLK_CAL_GEN_1_TIME_B0_7_0LN_TOTAL_CAL_DUR_TIME_B3_7_0LN_TOTAL_CAL_DUR_TIME_B2_7_0LN_TOTAL_CAL_DUR_TIME_B1_7_0LN_TOTAL_CAL_DUR_TIME_B0_7_0SPD_TO_TGT_SPEED_TIME_B3_7_0SPD_TO_TGT_SPEED_TIME_B2_7_0SPD_TO_TGT_SPEED_TIME_B1_7_0SPD_TO_TGT_SPEED_TIME_B0_7_0SELLV_VREF_FW_CONT_CAL_EN_7_0TX_VREF_SEL_POWER_UP_VAL_7_0[07:00] START_7_0: 0x%05x FBNIC_PCIE_AP_ARG: 0x%08x [15:00] AP_ARG_15_0: 0x%05x [31:16] %s: 0x%05x [15:00] %s: 0x%05x [31:16] VCON_15_0: 0x%05x FBNIC_PCIE_TEST0: 0x%08x FBNIC_PCIE_TEST2: 0x%08x FBNIC_PCIE_TEST3: 0x%08x FBNIC_PCIE_TEST4: 0x%08x FBNIC_PCIE_TEST5: 0x%08x FBNIC_PCIE_SYS_REG: 0x%08x [31:28] LN_SEL_3_0: 0x%02x [27:27] BROADCAST: 0x%02x [09:09] IDDQ: 0x%02x [00:00] EN_CMN: 0x%02x FBNIC_PCIE_CMN_REG1: 0x%08x FBNIC_PCIE_CMN_REG0: 0x%08x [00:00] TRAIN_SIM_EN: 0x%02x FBNIC_PCIE_CID_REG0: 0x%08x [31:28] CID0_7_4: 0x%02x [27:24] CID0_3_0: 0x%02x [23:20] CID1_7_4: 0x%02x [19:16] CID1_3_0: 0x%02x FBNIC_PCIE_CID_REG1: 0x%08x [31:29] PHY_NUM_2_0: 0x%02x [28:26] AVDD_SEL_2_0: 0x%02x [24:24] BG_RDY: 0x%02x [14:12] PHY_MODE_2_0: 0x%02x [07:04] SPD_CFG_3_0: 0x%02x [02:02] PU_IVREF: 0x%02x [14:14] FW_READY: 0x%02x BYPASS_SPEED_TABLE_LOAD_DIS[08:08] CAL_DONE: 0x%02x [07:07] RX_CAL_DONE: 0x%02x [06:06] TX_CAL_DONE: 0x%02x [00:00] PIPE4_EN: 0x%02x FBNIC_PCIE_MCU_CONF: 0x%08x [08:08] MODE_EN_CMN: 0x%02x COMMON_CONF_UPDATE_DONE_7_0MCU_SOFT_RST_OCCURRED_LN0_7_0MCU_SOFT_RST_OCCURRED_LN1_7_0MCU_SOFT_RST_OCCURRED_LN2_7_0MCU_SOFT_RST_OCCURRED_LN3_7_0REFCLK_DIS_FALLING_QUERY_7_0[15:08] AVDD_SEL_7_0: 0x%05x [07:00] SEL_VAL_7_0: 0x%05x [15:08] CAL_SUPP_7_0: 0x%05x ALL_TOTAL_CAL_DUR_TIME_B3_7_0ALL_TOTAL_CAL_DUR_TIME_B2_7_0ALL_TOTAL_CAL_DUR_TIME_B1_7_0ALL_TOTAL_CAL_DUR_TIME_B0_7_0eD@????=M=<;m;::o9*9K7\ \[ZZ#XUASRR,RQbQQrPOOqNMMFMZLLKKJXJ JGDA@Pi$4g߱{}2[Azá;Wߛ? bXʓ@ Ƒ^ӐIy4̎t/_n&0@tх'}ڃ0m v~}}]|{ {fzyyoxwwqvuuQtsrq!qUponnGm{lkk9jmihg g_feevdccBba`K`__b^]87]6F655@5xxxRxxxxxQx xxxxxxxxxxxxxx_xxxx5xxxxxJ?*x xxxxxxx 8 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxZ xxxxxxxxx xxxxxxJxxxx m N,xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxlxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxg$TTTTTTT\TTTTTTTTTTTTT$|,4TTTTTtTTTTTTTTTTTTTTTTTTTTTTT4|TLL|,4$TllT<tL$\L+{n e zn*data size versus registers read mismatch received unexpected message: len=%u type=%u cmd=%u check failed FBNIC_CSR_PUL_USER check failed FBNIC_CSR_END_PUL_USER FBNIC_PUL_USER_SCRATCH: 0x%08x FBNIC_PUL_USER_IB_OB_ERR0_INTR_STS: 0x%08x [00:00] OB_WR_STG_UF: 0x%02x [01:01] OB_WR_DATA_UF: 0x%02x [02:02] OB_WR_CTRL_UF: 0x%02x [03:03] OB_CPL_STAT_NOT_SC: 0x%02x [04:04] OB_CPL_INV_BC: 0x%02x [05:05] OB_CPL_UC_ATTR: 0x%02x [06:06] OB_CPL_UC_ADDR: 0x%02x [07:07] OB_CPL_BC_TOO_BIG: 0x%02x [09:09] OB_CPL_ABORT: 0x%02x [10:10] OB_CPL_LOGIC_ERR: 0x%02x [11:11] OB_CPL_POISONED: 0x%02x [12:12] OB_CPL_DATA_OF: 0x%02x [13:13] OB_CPL_CNTX_OF: 0x%02x [18:18] MSI_X_ECC_ERR: 0x%02x [19:19] MSI_X_CRC_ERR: 0x%02x [20:20] IB_SEQ_CDC_FIFO_OF: 0x%02x [21:21] IB_CSR_P_CRDT_CDC_UF: 0x%02x [22:22] IB_CSR_MWR_DMA: 0x%02x [23:23] IB_ZERO_BYTE_WR: 0x%02x [24:24] OB_CPL_INV_TAG: 0x%02x FBNIC_PUL_USER_IB_OB_ERR0_INTR_MASK: 0x%08x FBNIC_PUL_USER_ERR1_INTR_STS: 0x%08x [00:00] IB_UNSUP_REQ: 0x%02x [01:01] IB_UNSUP_ALIGN: 0x%02x [02:02] IB_CSR_WR_TLP_ERR: 0x%02x [03:03] IB_CSR_P_FIFO_OF: 0x%02x [04:04] IB_DURGA_P_CDC_OF: 0x%02x [05:05] IB_DURGA_P_CRDT_CDC_UF: 0x%02x [06:06] IB_DURGA_MWR_NON_CONT_BE: 0x%02x [07:07] IB_DMA_ACK_UF: 0x%02x [08:08] IB_DURGA_WR_ZERO_BYTE: 0x%02x [09:09] IB_DURGA_WR_TLP_ERR: 0x%02x [10:10] IB_DURGA_RD_UR_ERR: 0x%02x [11:11] IB_DURGA_RD_TLP_ERR: 0x%02x [12:12] IB_DURGA_RD_REQ_OF: 0x%02x [13:13] IB_DURGA_RD_REQ_UF: 0x%02x [14:14] IB_DURGA_NP_CDC_OF: 0x%02x [15:15] IB_DURGA_NP_CPL_ECC_SEC: 0x%02x [16:16] IB_DURGA_NP_CPL_ECC_DED: 0x%02x [17:17] IB_DURGA_NP_CPL_OF: 0x%02x [18:18] IB_DURGA_NP_CPL_DATA_UF: 0x%02x [19:19] IB_DURGA_NP_CPL_CDC_UF: 0x%02x [20:20] IB_DURGA_NP_CPL_CNTX_UF: 0x%02x [21:21] IB_DURGA_NP_CPL_DW_CNT_OF: 0x%02x [22:22] IB_DURGA_NP_CPL_DW_CNT_UF: 0x%02x [23:23] XALI_IB_CSR_NP_STG_OF: 0x%02x [24:24] XALI_IB_CSR_NP_STG_UF: 0x%02x [25:25] XALI_IB_DURGA_NP_STG_OF: 0x%02x [26:26] XALI_IB_DURGA_NP_STG_UF: 0x%02x [27:27] XALI_IB_CDC_OF: 0x%02x [28:28] XALI_IB_CDC_UF: 0x%02x [29:29] IB_NP_CNTX_ECC_SEC: 0x%02x [30:30] IB_NP_CNTX_ECC_DED: 0x%02x FBNIC_PUL_USER_IB_OB_ERR1_INTR_MASK: 0x%08x FBNIC_PUL_USER_IP_SMLH_RST_INTR_STS [00:00] SMLH_REQ_RST_NOT_RISE: 0x%02x [01:01] SMLH_REQ_RST_NOT_FALL: 0x%02x FBNIC_PUL_USER_IP_SMLH_RST_INTR_MASKFBNIC_PUL_USER_IP_DMA_INTR_STS: 0x%08x FBNIC_PUL_USER_IP_DMA_INTR_MASK: 0x%08x FBNIC_PUL_USER_IP_CFG_STAT_RISE_INTR_STS [05:05] ADVISORY_NF_STS: 0x%02x [06:06] EMERGENCY_PWR_RED_DET: 0x%02x FBNIC_PUL_USER_IP_CFG_STAT_RISE_INTR_MASKFBNIC_PUL_USER_IP_CFG_STAT_FALL_INTR_STSFBNIC_PUL_USER_IP_CFG_STAT_FALL_INTR_MASKFBNIC_PUL_USER_IP_PWR_MGMT_RISE_INTR_STS [00:00] PM_LINKST_IN_L1: 0x%02x [01:01] PM_L1_ENTRY_STARTED: 0x%02x [02:02] PM_ASPM_L1_ENTER_READY: 0x%02x [03:03] PM_LINKST_IN_L2: 0x%02x [04:04] PM_LINKST_L2_EXIT: 0x%02x [06:06] PM_LINKST_IN_L0S: 0x%02x [08:08] RADM_SLOT_PWR_LIMIT: 0x%02x FBNIC_PUL_USER_IP_PWR_MGMT_RISE_INTR_MASKFBNIC_PUL_USER_IP_PWR_MGMT_FALL_INTR_STSFBNIC_PUL_USER_IP_PWR_MGMT_FALL_INTR_MASKFBNIC_PUL_USER_IP_LINK_RST_RISE_INTR_STS [00:00] LINK_REQ_RST_NOT: 0x%02x [01:01] SMLH_LINK_UP: 0x%02x [02:02] RDLH_LINK_UP: 0x%02x [04:04] FLR_PF_ACTIVE: 0x%02x FBNIC_PUL_USER_IP_LINK_RST_RISE_INTR_MASKFBNIC_PUL_USER_IP_LINK_RST_FALL_INTR_STSFBNIC_PUL_USER_IP_LINK_RST_FALL_INTR_MASKFBNIC_PUL_USER_IP_PTM_RISE_INTR_STS [00:00] PTM_RESP_RDY_TO_VALIDATE: 0x%02x [01:01] PTM_TRIGGER_ALLOWED: 0x%02x [02:02] PTM_UPDATING: 0x%02x FBNIC_PUL_USER_IP_PTM_RISE_INTR_MASKFBNIC_PUL_USER_IP_PTM_FALL_INTR_STSFBNIC_PUL_USER_IP_PTM_FALL_INTR_MASKFBNIC_PUL_USER_IP_ERR_INTR_STS: 0x%08x [00:00] RCVR_ERR_STS: 0x%02x [01:01] BAD_TLP_ERR_STS: 0x%02x [02:02] REPLAY_TO_ERR_STS: 0x%02x [03:03] ECRC_ERR_STS: 0x%02x [04:04] CORRECTED_INTERN_ERR_STS: 0x%02x [05:05] DL_PROTO_ERR_STS: 0x%02x [06:06] FC_PROTO_ERR_STS: 0x%02x [07:07] UNCOR_INTERN_ERR_STS: 0x%02x [08:08] MLF_TLP_ERR_STS: 0x%02x [09:09] RADM_QOVERFLOW: 0x%02x [10:10] RADM_MSG_UNLOCK: 0x%02x [11:11] RADM_CPL_TO: 0x%02x [12:12] TRGT_CPL_TO: 0x%02x [15:13] APP_PARITY_ERRS: 0x%02x [16:16] RASDP_ERR_MODE_RISE: 0x%02x [17:17] RASDP_ERR_MODE_FALL: 0x%02x [19:18] RADM_RCVD_CFG0WR_POISONED: 0x%02x [21:20] RADM_RCVD_CFG1WR_POISONED: 0x%02x [22:22] USP_EQ_REDO_EXECUTED: 0x%02x [23:23] BAD_DLLP_ERR_STS: 0x%02x FBNIC_PUL_USER_IP_ERR_INTR_MASK: 0x%08x FBNIC_PUL_USER_IP_MISC_INTR_STS: 0x%08x [00:00] PWR_BUDGET_SEL: 0x%02x [02:02] RADM_PM_TURNOFF: 0x%02x [03:03] RADM_SLOT_PWR_LIMIT: 0x%02x [04:04] PTM_CNTX_VALID: 0x%02x [05:05] PTM_CLOCK_UPDATED: 0x%02x [06:06] PTM_REQ_RESPONSE_TO: 0x%02x [07:07] PTM_REQ_DUP_RX: 0x%02x [08:08] PTM_REQ_REPLAY_TX: 0x%02x RADM_TRGT1_HDR_MULERROR_COREOUTPUTERR_DETECT_EDMARBUFF2RAM_ADDRAERR_MULTPL_EDMARBUFF2RAM_ADDRAERR_DETECT_EDMARBUFF2RAM_ADDRBERR_MULTPL_EDMARBUFF2RAM_ADDRB [21:21] ROM_RD_PRAM_WR_DONE: 0x%02x FBNIC_PUL_USER_IP_MISC_INTR_MASKFBNIC_PUL_USER_IP_CORE_CFG: 0x%08x [00:00] PTM_AUTO_UPDATE_SIGNAL: 0x%02x [01:01] XALI_IB_SP_RR_MODE: 0x%02x [08:02] HALT_THRESH: 0x%05x [15:09] NP_HALT_THRESH: 0x%05x [22:16] P_HALT_THRESH: 0x%05x [31:23] HALT_DURGA_DATA_THRESH: 0x%05x FBNIC_PUL_USER_IP_FLR_DONE_PTM_PULSE [00:00] APP_FLR_PF_DONE: 0x%02x [01:01] MANUAL_UPDATE_PULSE: 0x%02x [02:02] EXTERNAL_MASTER_STROBE: 0x%02x FBNIC_PUL_USER_IP_CFG_INFO_STS: 0x%08x [00:00] BUS_MASTER_EN: 0x%02x [01:01] MEM_SPACE_EN: 0x%02x [15:11] PBUS_DEV_NUM: 0x%05x [18:18] ADVISORY_NF_STS: 0x%02x [19:19] HDR_LOG_OVERFLOW_STS: 0x%02x [25:20] NEG_LINK_WIDTH: 0x%05x [26:26] RASDP_ERROR_MODE: 0x%02x [27:27] EMERGENCY_PWR_RED_DET: 0x%02x FBNIC_PUL_USER_IP_PWR_MGMT_STS: 0x%08x [01:01] PM_LINKST_IN_L2: 0x%02x [04:02] PM_CURNT_STATE: 0x%02x [08:08] PM_LINKST_IN_L0S: 0x%02x [14:10] PM_MASTER_STATE: 0x%05x [19:15] PM_SLAVE_STATE: 0x%05x [20:20] PM_L1_ENTRY_STARTED: 0x%02x [21:21] PM_LINKST_L2_EXIT: 0x%02x [22:22] PM_ASPM_L1_ENTER_READY: 0x%02x FBNIC_PUL_USER_IP_RADM_SLOT_PWR_PAYLOADFBNIC_PUL_USER_IP_LINK_RST_STS: 0x%08x [00:00] SMLH_REQ_RST_NOT: 0x%02x [01:01] LINK_REQ_RST_NOT: 0x%02x [02:02] SMLH_LINK_UP: 0x%02x [03:03] RDLH_LINK_UP: 0x%02x [05:05] FLR_PF_ACTIVE: 0x%02x [06:06] APP_FLR_PF_DONE: 0x%02x [07:07] AW_FLUSH_DONE: 0x%02x [08:08] AR_FLUSH_DONE: 0x%02x [14:09] SMLH_LTSSM_STATE: 0x%05x [15:15] MSIX_BUFF_EMPTY: 0x%02x FBNIC_PUL_USER_IP_RX_QUEUE_STS: 0x%08x [00:00] RADM_Q_NOT_EMPTY: 0x%02x RADM_RCVD_CFGWR_POISONED_EXT_REG_NUMRADM_RCVD_CFGWR_POISONED_REG_NUMRADM_RCVD_CFGWR_POISONED_FUNC_NUMFBNIC_PUL_USER_IP_PTM_STS: 0x%08x FBNIC_PUL_USER_IP_PTM_LOCAL_CLCK_L: 0x%08x FBNIC_PUL_USER_IP_PTM_LOCAL_CLCK_U: 0x%08x FBNIC_PUL_USER_IP_PTM_CLOCK_CORRECTION_LFBNIC_PUL_USER_IP_PTM_CLOCK_CORRECTION_UFBNIC_PUL_USER_IP_CXPL_DEBUG_INFO_LFBNIC_PUL_USER_IP_CXPL_DEBUG_INFO_UFBNIC_PUL_USER_IP_CXPL_DEBUG_INFO_EIFBNIC_PUL_USER_IB_TAG_POOL_0: 0x%08x FBNIC_PUL_USER_IB_TAG_POOL_1: 0x%08x FBNIC_PUL_USER_IB_ZERO_B_RD_ADDR: 0x%08x FBNIC_PUL_USER_OB_TLP_HDR_AW_CFG: 0x%08x [11:09] AW_TQM_ATTR: 0x%02x [14:12] AW_RQM_ATTR: 0x%02x [17:15] AW_RDE_ATTR: 0x%02x [20:20] AW_FLUSH_MODE: 0x%02x FBNIC_PUL_USER_OB_TLP_HDR_AR_CFG: 0x%08x [11:09] AR_TQM_ATTR: 0x%02x [14:12] AR_RQM_ATTR: 0x%02x [17:15] AR_TDE_ATTR: 0x%02x [22:22] AR_CPL_MODE: 0x%02x [23:23] AR_XALI_MODE: 0x%02x FBNIC_PUL_USER_OB_TLP_HDR_DURGA_AW_CFG [08:07] AW_TPH_TYPE: 0x%02x [16:09] AW_TPH_ST_TAG: 0x%05x FBNIC_PUL_USER_OB_TLP_HDR_DURGA_AR_CFG [08:07] AR_TPH_TYPE: 0x%02x [16:09] AR_TPH_ST_TAG: 0x%05x FBNIC_PUL_USER_OB_P_CRDTS_THRESH: 0x%08x FBNIC_PUL_USER_OB_CPL_THRESH: 0x%08x [18:08] DATA_THRESH: 0x%02x FBNIC_PUL_USER_OB_TAG_MAX_AVAIL: 0x%08x FBNIC_PUL_USER_OB_TAG_POOL_ENB%d: 0x%08x FBNIC_PUL_USER_OB_CTO_TAG_RST: 0x%08x FBNIC_PUL_USER_OB_DBG_P_U: 0x%08x FBNIC_PUL_USER_OB_DBG_P_L: 0x%08x FBNIC_PUL_USER_OB_LOCAL_P_CRDT: 0x%08x [15:00] LOCAL_PD_CRDTS: 0x%05x [27:16] LOCAL_PH_CRDTS: 0x%05x FBNIC_PUL_USER_OB_IP_P_CRDT: 0x%08x [11:00] IP_PD_CRDTS: 0x%05x [19:12] IP_PH_CRDTS: 0x%05x FBNIC_PUL_USER_OB_TAG_POOL_%d: 0x%08x FBNIC_PUL_USER_OB_TAG_POOL_ERR_%d: 0x%08x FBNIC_PUL_USER_OB_CTO_TAG_STAT: 0x%08x [24:16] TAGS_IN_LOCK: 0x%05x [08:00] TAGS_IN_FLIGHT: 0x%05x FBNIC_PUL_USER_OB_IP_NP_HDR_CRDTS: 0x%08x FBNIC_PUL_USER_OB_IP_CPL_BUFF_CRDTSFBNIC_PUL_USER_OB_LOCAL_NP_HDR_CRDTS: 0x%08x [15:12] NP_CRDTS_STS: 0x%05x FBNIC_PUL_USER_OB_LOCAL_CPL_BUFF_CRDTSFBNIC_PUL_USER_OB_CTO_STAT_%d: 0x%08x FBNIC_PUL_USER_OB_RD_TLP_CNT_31_0: 0x%08x FBNIC_PUL_USER_OB_RD_TLP_CNT_63_32: 0x%08x FBNIC_PUL_USER_OB_RD_DWORD_CNT_31_0: 0x%08x FBNIC_PUL_USER_OB_RD_DWORD_CNT_63_32FBNIC_PUL_USER_OB_WR_TLP_CNT_31_0: 0x%08x FBNIC_PUL_USER_OB_WR_TLP_CNT_63_32: 0x%08x FBNIC_PUL_USER_OB_WR_DWORD_CNT_31_0FBNIC_PUL_USER_OB_WR_DWORD_CNT_63_32FBNIC_PUL_USER_OB_CPL_TLP_CNT_31_0FBNIC_PUL_USER_OB_CPL_TLP_CNT_63_32FBNIC_PUL_USER_OB_CPL_DWORD_CNT_31_0FBNIC_PUL_USER_OB_CPL_DWORD_CNT_63_32FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_31_0FBNIC_PUL_USER_OB_RD_DBG_CNT_CPL_CRED_63_32FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_31_0FBNIC_PUL_USER_OB_RD_DBG_CNT_TAG_63_32FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_31_0FBNIC_PUL_USER_OB_RD_DBG_CNT_NP_CRED_63_32FBNIC_PUL_USER_OB_RD_CNTXT_DBG_FIFO_CNTFBNIC_PUL_USER_OB_RD_CNTXT_DBG_FIFO_POPFBNIC_PUL_USER_OB_RD_CNTXT_DBG_FIFOFBNIC_PUL_USER_IB_CSR_WR: 0x%08x FBNIC_PUL_USER_IB_CSR_RD: 0x%08x FBNIC_PUL_USER_IB_CSR_CPL: 0x%08x FBNIC_PUL_USER_IB_DURGA_WR: 0x%08x FBNIC_PUL_USER_IB_DURGA_RD: 0x%08x FBNIC_PUL_USER_IB_DMA_WR: 0x%08x FBNIC_PUL_USER_IB_DMA_RD: 0x%08x FBNIC_PUL_USER_IB_DMA_CPL: 0x%08x FBNIC_PUL_USER_IB_CSR_WR_DW_U: 0x%08x FBNIC_PUL_USER_IB_CSR_WR_DW_L: 0x%08x FBNIC_PUL_USER_IB_CSR_RD_DW_U: 0x%08x FBNIC_PUL_USER_IB_CSR_RD_DW_L: 0x%08x FBNIC_PUL_USER_IB_CSR_CPL_DW_U: 0x%08x FBNIC_PUL_USER_IB_CSR_CPL_DW_L: 0x%08x FBNIC_PUL_USER_IB_DURGA_WR_DW_CNT_UFBNIC_PUL_USER_IB_DURGA_WR_DW_CNT_LFBNIC_PUL_USER_IB_DURGA_RD_DW_CNT_UFBNIC_PUL_USER_IB_DURGA_RD_DW_CNT_LFBNIC_PUL_USER_IB_DURGA_CPL_DW_CNT_UFBNIC_PUL_USER_IB_DURGA_CPL_DW_CNT_LFBNIC_PUL_USER_IB_DMA_WR_DW_U: 0x%08x FBNIC_PUL_USER_IB_DMA_WR_DW_L: 0x%08x FBNIC_PUL_USER_IB_DMA_RD_DW_U: 0x%08x FBNIC_PUL_USER_IB_DMA_RD_DW_L: 0x%08x FBNIC_PUL_USER_IB_DMA_CPL_DW_U: 0x%08x FBNIC_PUL_USER_IB_DMA_CPL_DW_L: 0x%08x FBNIC_PUL_USER_IB_CSR_WR_TLP_ERR_CNTFBNIC_PUL_USER_IB_CSR_RD_TLP_ERR_CNTFBNIC_PUL_USER_IB_CSR_CPL_TLP_ERR_CNTFBNIC_PUL_USER_IB_DURGA_WR_TLP_ERR_CNTFBNIC_PUL_USER_IB_DURGA_RD_TLP_ERR_CNTFBNIC_PUL_USER_IB_DURGA_CPL_TLP_ERR_CNTFBNIC_PUL_USER_IB_DMA_WR_TLP_ERR_CNTFBNIC_PUL_USER_IB_DMA_RD_TLP_ERR_CNTFBNIC_PUL_USER_IB_DMA_CPL_TLP_ERR_CNTFBNIC_PUL_USER_IB_CSR_WR_DW_ERR_CNTFBNIC_PUL_USER_IB_CSR_RD_DW_ERR_CNTFBNIC_PUL_USER_IB_CSR_CPL_DW_ERR_CNTFBNIC_PUL_USER_IB_DURGA_WR_DW_ERR_CNTFBNIC_PUL_USER_IB_DURGA_RD_DW_ERR_CNTFBNIC_PUL_USER_IB_DURGA_CPL_DW_ERR_CNTFBNIC_PUL_USER_IB_DMA_WR_DW_ERR_CNTFBNIC_PUL_USER_IB_DMA_RD_DW_ERR_CNTFBNIC_PUL_USER_IB_DMA_CPL_DW_ERR_CNTFBNIC_PUL_USER_PERF_CFG: 0x%08x [01:00] IB_PATH_SEL: 0x%02x [03:02] XALI_INTF_BW_SEL: 0x%02x [06:04] TRGT1_HALT_CTRL: 0x%02x FBNIC_PUL_USER_PERF_ITER_CNT_WIN0: 0x%08x FBNIC_PUL_USER_PERF_ITER_CNT_WIN1: 0x%08x FBNIC_PUL_USER_PERF_TLP_WIN0_%d: 0x%08x FBNIC_PUL_USER_PERF_TLP_WIN1_%d: 0x%08x FBNIC_PUL_USER_PERF_DW_U_WIN0_%d: 0x%08x FBNIC_PUL_USER_PERF_DW_L_WIN0_%d: 0x%08x FBNIC_PUL_USER_PERF_DW_U_WIN1_%d: 0x%08x FBNIC_PUL_USER_PERF_DW_L_WIN1_%d: 0x%08x FBNIC_PUL_USER_PERF_BW_U_WIN0_%d: 0x%08x FBNIC_PUL_USER_PERF_BW_L_WIN0_%d: 0x%08x FBNIC_PUL_USER_PERF_BW_U_WIN1_%d: 0x%08x FBNIC_PUL_USER_PERF_BW_L_WIN1_%d: 0x%08x FBNIC_PUL_USER_PCIE_SS_SPARE0: 0x%08x FBNIC_PUL_USER_PCIE_SS_SPARE1: 0x%08x FBNIC_PUL_USER_PCIE_SS_SPARE2: 0x%08x FBNIC_PUL_USER_PCIE_SS_SPARE3: 0x%08x length failed FBNIC_CSR_END_PUL_USER check failed FBNIC_CSR_START_QUEUE check failed FBNIC_CSR_END_QUEUE [02:02] PREFETCH_DISABLE: 0x%02x [30:29] TXB_FIFO_SEL: 0x%02x [31:31] AGGREGATION_MODE: 0x%02x [00:00] TRANSACTION_PENDING: 0x%02x [01:01] DISABLED_ON_ERR: 0x%02x [15:08] PREFETCH_FIFO_RDPTR: 0x%05x [23:16] PREFETCH_FIFO_WRPTR: 0x%05x [31:24] TDF_PREFETCH_CNT: 0x%05x [07:00] TDF_FRAME_CNT: 0x%08x [11:11] BASE_MEM_DBE: 0x%02x [10:10] BASE_MEM_SBE: 0x%02x [09:09] PREFETCH_DBE: 0x%02x [08:08] PREFETCH_SBE: 0x%02x [07:07] PREFETCH_FIFO_UF: 0x%02x [06:06] PREFETCH_FIFO_OF: 0x%02x [01:00] RD_AXI_ERRS: 0x%02x [05:05] PREFETCH_DBE: 0x%02x [04:04] PREFETCH_SBE: 0x%02x FBNIC_QUEUE_TDE_TYPE1_CMPL_REQFBNIC_QUEUE_TCQ_CTL[%d]: 0x%08x FBNIC_QUEUE_TCQ_PTRS[%d]: 0x%08x FBNIC_QUEUE_TCQ_STS[%d]: 0x%08x [14:08] TCD_COAL_FIFO_RDPTR: 0x%05x [22:16] TCD_COAL_FIFO_WRPTR: 0x%05x [31:24] TCD_COAL_CNT: 0x%05x FBNIC_QUEUE_TCQ_SIZE[%d]: 0x%08x FBNIC_QUEUE_TCQ_ERR_INTR_STS[%d]: 0x%08x [02:02] TCQ_ALMOST_FULL: 0x%02x [08:08] COALESCE_SBE: 0x%02x [09:09] COALESCE_DBE: 0x%02x FBNIC_QUEUE_TCQ_BAL[%d]: 0x%08x FBNIC_QUEUE_TCQ_BAH[%d]: 0x%08x FBNIC_QUEUE_TIM_CTL[%d]: 0x%08x [07:00] MSIX_VECTOR: 0x%05x FBNIC_QUEUE_TIM_THRESHOLD[%d]: 0x%08x [14:00] TWD_THRESHOLD: 0x%05x FBNIC_QUEUE_TIM_CLEAR[%d]: 0x%08x FBNIC_QUEUE_TIM_MASK[%d]: 0x%08x FBNIC_QUEUE_TIM_TIMER[%d]: 0x%08x FBNIC_QUEUE_TIM_COUNTS[%d]: 0x%08x FBNIC_QUEUE_RCQ_CTL[%d]: 0x%08x FBNIC_QUEUE_RCQ_PTRS[%d]: 0x%08x FBNIC_QUEUE_RCQ_STS[%d]: 0x%08x [14:08] RCD_COALESCE_FIFO_RDPTR: 0x%05x [22:16] RCD_COALESCE_FIFO_WRPTR: 0x%05x [31:24] RCD_COALESCE_CNT: 0x%08x FBNIC_QUEUE_RCQ_SIZE[%d]: 0x%08x FBNIC_QUEUE_RCQ_ERR_INTR_STS[%d]: 0x%08x [12:12] UNEXP_RCD_ERR: 0x%08x [11:11] BASE_MEM_DBE: 0x%08x [10:10] BASE_MEM_SBE: 0x%08x [08:08] COALESCE_SBE: 0x%08x [09:09] COALESCE_DBE: 0x%08x [01:00] WR_AXI_ERRS: 0x%08x [02:02] RCQ_ALMOST_FULL: 0x%08x FBNIC_QUEUE_RCQ_BAL[%d]: 0x%08x FBNIC_QUEUE_RCQ_BAH[%d]: 0x%08x FBNIC_QUEUE_BDQ_CTL[%d]: 0x%08x [02:02] PRE_DISABLE: 0x%02x FBNIC_QUEUE_BDQ_HPQ_PTRS[%d]: 0x%08x FBNIC_QUEUE_BDQ_PPQ_PTRS[%d]: 0x%08x FBNIC_QUEUE_BDQ_HPQ_STS[%d]: 0x%08x [31:24] PAGES_PREFETCH_CNT: 0x%05x FBNIC_QUEUE_BDQ_PPQ_STS[%d]: 0x%08x [15:08] PRE_FIFO_RDPTR: 0x%05x [23:16] PRE_FIFO_WRPTR: 0x%05x [31:24] PAGES_PRE_CNT: 0x%05x FBNIC_QUEUE_BDQ_HPQ_SIZE[%d]: 0x%08x FBNIC_QUEUE_BDQ_PPQ_SIZE[%d]: 0x%08x FBNIC_QUEUE_BDQ_HPQ_ERR_INTR_STS[%d]: 0x%08x [00:00] BDQ_ALMOST_EMPTY: 0x%02x [02:01] RD_AXI_ERRS: 0x%02x [06:06] PREFETCH_FIFO_OVERFLOW: 0x%02x [07:07] PREFETCH_FIFO_UNDERFLOW: 0x%02x FBNIC_QUEUE_BDQ_PPQ_ERR_INTR_STS[%d]: 0x%08x FBNIC_QUEUE_BDQ_HPQ_BAL[%d]: 0x%08x FBNIC_QUEUE_BDQ_HPQ_BAH[%d]: 0x%08x FBNIC_QUEUE_BDQ_PPQ_BAL[%d]: 0x%08x FBNIC_QUEUE_BDQ_PPQ_BAH[%d]: 0x%08x FBNIC_QUEUE_RDE_ERR_INTR_STS[%d]: 0x%08x [03:03] CONTEXT_DBE: 0x%08x [02:02] CONTEXT_SBE: 0x%08x FBNIC_QUEUE_RDE_CTL0[%d]: 0x%08x [19:11] MIN_TAIL_ROOM: 0x%05x [28:20] MIN_HEAD_ROOM: 0x%05x [31:31] ENABLE_HEADER_SPLIT: 0x%02x FBNIC_QUEUE_RDE_CTL1[%d]: 0x%08x [24:12] MAX_HEADER_BYTES: 0x%08x [11:09] PAYLOAD_OFFSET_ALIGN: 0x%08x [08:06] PAYLOAD_PAGE_CLOSE_THRESH: 0x%08x [01:00] PAYLOAD_PACK_MODE: 0x%08x FBNIC_QUEUE_RDE_PKT_CNT[%d]: 0x%08x FBNIC_QUEUE_RDE_PKT_ERR_CNT[%d]: 0x%08x FBNIC_QUEUE_RDE_CQ_DROP_CNT[%d]: 0x%08x FBNIC_QUEUE_RDE_BDQ_DROP_CNT[%d]: 0x%08x FBNIC_QUEUE_RDE_BYTE_CNT_L[%d]: 0x%08x FBNIC_QUEUE_RDE_BYTE_CNT_H[%d]: 0x%08x FBNIC_QUEUE_RIM_CTL[%d]: 0x%08x [07:00] MSIX_VECTOR: 0x%08x FBNIC_QUEUE_RIM_THRESHOLD[%d]: 0x%08x [14:00] RCD_THRESHOLD: 0x%08x FBNIC_QUEUE_RIM_CLEAR[%d]: 0x%08x FBNIC_QUEUE_RIM_MASK[%d]: 0x%08x FBNIC_QUEUE_RIM_COAL_STATUS[%d]: 0x%08x length failed FBNIC_CSR_END_QUEUE check failed FBNIC_CSR_START_SIG check failed FBNIC_CSR_END_SIG [00:00] EMAC_CF_GEN_REQ: 0x%02x [01:01] EMAC_TX_LI_FAULT: 0x%02x [02:02] EMAC_TX_REM_FAULT: 0x%02x [03:03] EMAC_TX_LOC_FAULT: 0x%02x [04:04] EMAC_LPI_TXHOLD: 0x%02x [05:05] EMAC_LOWP_ENA: 0x%02x [06:06] EMAC_PFC_MODE: 0x%02x [07:07] EMAC_MAC_PAUSE_EN: 0x%02x [08:08] EMAC_TX_CRC: 0x%02x [09:09] EMAC_TX_STOP: 0x%02x [10:10] EMAC_CFG_MODE128: 0x%02x [11:11] EMAC_RESET_RXCLK: 0x%02x [12:12] EMAC_RESET_TXCLK: 0x%02x [13:13] EMAC_RESET_FF_RX_CLK: 0x%02x [14:14] EMAC_RESET_FF_TX_CLK: 0x%02x [15:15] EMAC_RX2TX_LPBK_EN: 0x%02x [15:00] EMAC_CF_MACDA1: 0x%02x [15:00] EMAC_CF_ETYPE: 0x%02x [15:00] EMAC_CF_OCODE: 0x%05x [15:00] EMAC_CF_CDATA: 0x%05x [00:00] EMAC_CF_GEN_ACK: 0x%02x [01:01] EMAC_TX_EMPTY: 0x%02x [02:02] EMAC_TX_ISIDLE: 0x%02x [03:03] EMAC_MAC_ENABLE: 0x%02x [06:06] PCS100_ENA_IN0: 0x%02x [07:07] RXLAUI_ENA_IN0: 0x%02x [08:08] FEC91_1LANE_IN2: 0x%02x [09:09] FEC91_1LANE_IN0: 0x%02x [22:21] RESET_SD_RX_CLK: 0x%02x [24:23] RESET_SD_TX_CLK: 0x%02x [25:25] RESET_F91_REF_CLK: 0x%02x [26:26] RESET_XPCS_REF_CLK: 0x%02x [27:27] RESET_REF_CLK: 0x%02x [00:00] PCS_RSFEC_ALIGNED: 0x%02x [04:01] PCS_AMPS_LOCK: 0x%02x [24:05] PCS_BLOCK_LOCK: 0x%02x [26:26] PCS_ALIGN_DONE: 0x%02x [27:27] PCS_LINK_STATUS: 0x%02x [07:00] PCS_MAC0_RES_SPEED: 0x%02x [11:08] PCS_FEC_LOCKED: 0x%02x [00:00] TX_DATA_SEL: 0x%02x [01:01] SELECTOR_OVERRIDE: 0x%02x [02:02] LINK_STS_OVERRIDE: 0x%02x [03:03] ANEG_RESET_SD_TX_CLK: 0x%02x [04:04] ANEG_RESET_SD_RX_CLK: 0x%02x [05:05] ANEG_AN_SD25_TX_ENA: 0x%02x [06:06] ANEG_AN_SD25_RX_ENA: 0x%02x [07:07] ANEG_SD_TX_CLK_ENA: 0x%02x [08:08] ANEG_SD_RX_CLK_ENA: 0x%02x [09:09] ANEG_SD_SIGNAL: 0x%02x [10:10] ANEG_LINK_STATUS: 0x%02x [11:11] ANEG_LINK_STATUS_KX4: 0x%02x [12:12] ANEG_LINK_STATUS_2D5KX: 0x%02x [13:13] ANEG_LINK_STATUS_KX: 0x%02x [14:14] ANEG_AN_DIS_TIMER: 0x%02x [15:15] ANEG_AN_ENA: 0x%02x [00:00] ANEG_AN_TR_DIS_STATUS: 0x%02x [05:01] ANEG_AN_SELECT: 0x%02x [06:06] ANEG_AN_STATUS: 0x%02x [07:07] ANEG_AN_INT: 0x%02x [08:08] ANEG_AN_DONE: 0x%02x [09:09] ANEG_AN_VAL: 0x%02x [13:10] ANEG_AN_STATE: 0x%02x [14:14] ANEG_AN_RS_FEC_INT_ENA: 0x%02x [15:15] ANEG_AN_RS_FEC_ENA: 0x%02x [16:16] ANEG_AN_FEC_ENA: 0x%02x FBNIC_SIG_COMPHY_INTR_STS: 0x%08x FBNIC_SIG_COMPHY_INTR_SET: 0x%08x FBNIC_SIG_COMPHY_INTR_MASK: 0x%08x [01:01] SQ_DETECT0_INT_RISE: 0x%02x [02:02] SQ_DETECT0_INT_FALL: 0x%02x [03:03] SQ_DETECT1_INT_RISE: 0x%02x [04:04] SQ_DETECT1_INT_FALL: 0x%02x FBNIC_SIG_ANEG_INTR_STS: 0x%08x FBNIC_SIG_ANEG_INTR_SET: 0x%08x FBNIC_SIG_ANEG_INTR_MASK: 0x%08x [00:00] ANEG_AN_INT: 0x%02x [01:01] ANEG_AN_DONE: 0x%02x FBNIC_SIG_PCS_INTR_STS: 0x%08x FBNIC_SIG_PCS_INTR_SET: 0x%08x FBNIC_SIG_PCS_INTR_MASK: 0x%08x [00:00] PCS_POSEDGE_LINK_STATUS: 0x%02x [01:01] PCS_NEGEDGE_LINK_STATUS: 0x%02x [02:02] PCS_POSEDGE_ALIGN_DONE: 0x%02x [03:03] PCS_NEGEDGE_ALIGN_DONE: 0x%02x [04:04] PCS_POSEDGE_HI_BER: 0x%02x [05:05] PCS_NEGEDGE_HI_BER: 0x%02x [06:06] PCS_FEC_CERR: 0x%02x [07:07] PCS_FEC_NCERR: 0x%02x FBNIC_SIG_MAC_INTR_STS: 0x%08x FBNIC_SIG_MAC_INTR_SET: 0x%08x FBNIC_SIG_MAC_INTR_MASK: 0x%08x [00:00] TX_UNDERFLOW: 0x%02x [06:06] EMAC_REG_TS_AVAIL: 0x%02x [07:07] RX2TX_LPBK_FIFO_OVFL: 0x%02x [08:08] RX2TX_LPBK_FIFO_UNFL: 0x%02x [00:00] PCS_FEC_CERR: 0x%02x [01:01] PCS_FEC_NCERR: 0x%02x [00:00] OVERRIDE_EN: 0x%02x [01:01] OVERRIDE_VAL: 0x%02x [02:02] BLINK_RATE_MASK: 0x%02x FBNIC_SIG_PHY_SIG_DETECT: 0x%08x [01:00] PCS_SIGNAL_DET: 0x%02x [05:04] REPL_SIGNAL_W_SQ_DET: 0x%02x [08:08] COMPHY_SQ_DET0: 0x%02x [09:09] COMPHY_SQ_DET1: 0x%02x [07:04] FEC91_LL_MODE_I: 0x%02x [23:20] FEC_ERR_ENA: 0x%02x FBNIC_SIG_DEBUG_SEL_REG: 0x%08x [03:00] DATA_GROUPING_SEL: 0x%02x [07:04] DATA_BYTE_SEL: 0x%02x [31:08] DEBUG_SPARE: 0x%02x [03:03] DESK_LANE0_MEM0: 0x%02x [04:04] DESK_LANE0_MEM1: 0x%02x [05:05] DESK_LANE1_MEM0: 0x%02x [06:06] DESK_LANE1_MEM1: 0x%02x [13:13] FM_LANE0_MEM0: 0x%02x [14:14] FM_LANE0_MEM1: 0x%02x [15:15] FM_LANE1_MEM0: 0x%02x [16:16] FM_LANE1_MEM1: 0x%02x [17:17] FDM_LANE0_MEM0: 0x%02x [18:18] FDM_LANE0_MEM1: 0x%02x [19:19] FDM_LANE1_MEM0: 0x%02x [20:20] FDM_LANE1_MEM1: 0x%02x length failed FBNIC_CSR_END_SIG Error: op policy map not present Error: no policy index in what was expected to be ethtool header attribute Error: validation mask not reported for ethtool header flags malformed netlink message (bitset) malformed netlink message (pause modes) kernel device name too long: '%s' ethtool: message too short (%u bytes) invalid SecureOn password length %u (should be %u) Current message level: 0x%1$08x (%1$u) malformed netlink message (link_modes) Supports auto-negotiation: %s Advertised auto-negotiation: %s Link partner advertised link modes: link-partner-advertised-link-modeslink-partner-advertised-pause-frame-useLink partner advertised pause frame use: link-partner-advertised-auto-negotiationLink partner advertised FEC modes: link-partner-advertised-fec-modes Link partner advertised auto-negotiation: %s deprecated parameter '%s' not supported by kernel NL_POLICY_TYPE_ATTR_MIN_VALUE_SNL_POLICY_TYPE_ATTR_MAX_VALUE_SNL_POLICY_TYPE_ATTR_MIN_VALUE_UNL_POLICY_TYPE_ATTR_MAX_VALUE_UNL_POLICY_TYPE_ATTR_MIN_LENGTHNL_POLICY_TYPE_ATTR_MAX_LENGTHNL_POLICY_TYPE_ATTR_POLICY_IDXNL_POLICY_TYPE_ATTR_POLICY_MAXTYPENL_POLICY_TYPE_ATTR_BITFIELD32_MASKETHTOOL_A_TUNNEL_UDP_ENTRY_UNSPECETHTOOL_A_TUNNEL_UDP_ENTRY_PORTETHTOOL_A_TUNNEL_UDP_ENTRY_TYPEETHTOOL_A_CABLE_AMPLITUDE_UNSPECETHTOOL_A_CABLE_AMPLITUDE_PAIRETHTOOL_A_CABLE_STEP_FIRST_DISTANCEETHTOOL_A_CABLE_STEP_LAST_DISTANCEETHTOOL_A_CABLE_STEP_STEP_DISTANCEETHTOOL_A_CABLE_FAULT_LENGTH_UNSPECETHTOOL_A_CABLE_FAULT_LENGTH_PAIRETHTOOL_A_CABLE_FAULT_LENGTH_CMETHTOOL_A_CABLE_FAULT_LENGTH_SRCETHTOOL_A_STATS_GRP_HIST_BKT_LOWETHTOOL_A_STATS_GRP_HIST_BKT_HIETHTOOL_A_TUNNEL_UDP_TABLE_UNSPECETHTOOL_A_TUNNEL_UDP_TABLE_SIZEETHTOOL_A_TUNNEL_UDP_TABLE_TYPESETHTOOL_A_TUNNEL_UDP_TABLE_ENTRYETHTOOL_A_IRQ_MODERATION_UNSPECETHTOOL_A_IRQ_MODERATION_COMPSETHTOOL_A_CABLE_TDR_NEST_UNSPECETHTOOL_A_CABLE_TDR_NEST_AMPLITUDEETHTOOL_A_CABLE_TDR_NEST_PULSEETHTOOL_A_CABLE_NEST_FAULT_LENGTHETHTOOL_A_MM_STAT_REASSEMBLY_ERRORSETHTOOL_A_MM_STAT_REASSEMBLY_OKETHTOOL_A_MM_STAT_RX_FRAG_COUNTETHTOOL_A_MM_STAT_TX_FRAG_COUNTETHTOOL_A_C33_PSE_PW_LIMIT_UNSPECETHTOOL_A_C33_PSE_PW_LIMIT_MINETHTOOL_A_C33_PSE_PW_LIMIT_MAXETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWNETHTOOL_PODL_PSE_PW_D_STATUS_DISABLEDETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHINGETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERINGETHTOOL_PODL_PSE_PW_D_STATUS_SLEEPETHTOOL_PODL_PSE_PW_D_STATUS_IDLEETHTOOL_PODL_PSE_PW_D_STATUS_ERRORETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWNETHTOOL_PODL_PSE_ADMIN_STATE_DISABLEDETHTOOL_PODL_PSE_ADMIN_STATE_ENABLEDETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPECETHTOOL_A_CABLE_TEST_TDR_CFG_FIRSTETHTOOL_A_CABLE_TEST_TDR_CFG_LASTETHTOOL_A_CABLE_TEST_TDR_CFG_STEPETHTOOL_A_CABLE_TEST_TDR_CFG_PAIRETHTOOL_A_TS_HWTSTAMP_PROVIDER_UNSPECETHTOOL_A_TS_HWTSTAMP_PROVIDER_INDEXETHTOOL_A_TS_HWTSTAMP_PROVIDER_QUALIFIERETHTOOL_A_TS_STAT_TX_ONESTEP_PKTS_UNCONFIRMEDETHTOOL_A_PAUSE_STAT_TX_FRAMESETHTOOL_A_PAUSE_STAT_RX_FRAMESETHTOOL_A_PROFILE_IRQ_MODERATIONETHTOOL_TCP_DATA_SPLIT_UNKNOWNETHTOOL_TCP_DATA_SPLIT_DISABLEDETHTOOL_TCP_DATA_SPLIT_ENABLEDETHTOOL_A_STRINGSETS_STRINGSETETHTOOL_A_CABLE_TEST_TDR_UNSPECETHTOOL_A_CABLE_TEST_TDR_NTF_HEADERETHTOOL_A_CABLE_TEST_TDR_NTF_STATUSETHTOOL_A_CABLE_TEST_TDR_NTF_NESTETHTOOL_A_CABLE_TEST_NTF_UNSPECETHTOOL_A_CABLE_TEST_NTF_HEADERETHTOOL_A_CABLE_TEST_NTF_STATUSETHTOOL_A_TSCONFIG_HWTSTAMP_PROVIDERETHTOOL_A_TSCONFIG_HWTSTAMP_FLAGSETHTOOL_A_PHY_UPSTREAM_SFP_NAMEETHTOOL_A_PHY_DOWNSTREAM_SFP_NAMEETHTOOL_A_MODULE_FW_FLASH_UNSPECETHTOOL_A_MODULE_FW_FLASH_HEADERETHTOOL_A_MODULE_FW_FLASH_FILE_NAMEETHTOOL_A_MODULE_FW_FLASH_PASSWORDETHTOOL_A_MODULE_FW_FLASH_STATUSETHTOOL_A_MODULE_FW_FLASH_STATUS_MSGETHTOOL_A_MODULE_FW_FLASH_DONEETHTOOL_A_MODULE_FW_FLASH_TOTALETHTOOL_A_PODL_PSE_ADMIN_STATEETHTOOL_A_PODL_PSE_ADMIN_CONTROLETHTOOL_A_PODL_PSE_PW_D_STATUSETHTOOL_A_C33_PSE_ADMIN_CONTROLETHTOOL_A_C33_PSE_EXT_SUBSTATEETHTOOL_A_C33_PSE_AVAIL_PW_LIMITETHTOOL_A_C33_PSE_PW_LIMIT_RANGESETHTOOL_A_MODULE_POWER_MODE_POLICYETHTOOL_A_MODULE_EEPROM_UNSPECETHTOOL_A_MODULE_EEPROM_HEADERETHTOOL_A_MODULE_EEPROM_OFFSETETHTOOL_A_MODULE_EEPROM_LENGTHETHTOOL_A_MODULE_EEPROM_I2C_ADDRESSETHTOOL_A_TUNNEL_INFO_UDP_PORTSETHTOOL_A_CABLE_TEST_TDR_HEADERETHTOOL_A_TSINFO_HWTSTAMP_PROVIDERETHTOOL_A_COALESCE_RX_MAX_FRAMESETHTOOL_A_COALESCE_RX_USECS_IRQETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQETHTOOL_A_COALESCE_TX_MAX_FRAMESETHTOOL_A_COALESCE_TX_USECS_IRQETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQETHTOOL_A_COALESCE_STATS_BLOCK_USECSETHTOOL_A_COALESCE_USE_ADAPTIVE_RXETHTOOL_A_COALESCE_USE_ADAPTIVE_TXETHTOOL_A_COALESCE_PKT_RATE_LOWETHTOOL_A_COALESCE_RX_USECS_LOWETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOWETHTOOL_A_COALESCE_TX_USECS_LOWETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOWETHTOOL_A_COALESCE_PKT_RATE_HIGHETHTOOL_A_COALESCE_RX_USECS_HIGHETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGHETHTOOL_A_COALESCE_TX_USECS_HIGHETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGHETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVALETHTOOL_A_COALESCE_USE_CQE_MODE_TXETHTOOL_A_COALESCE_USE_CQE_MODE_RXETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTESETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMESETHTOOL_A_COALESCE_TX_AGGR_TIME_USECSETHTOOL_A_CHANNELS_COMBINED_MAXETHTOOL_A_CHANNELS_OTHER_COUNTETHTOOL_A_CHANNELS_COMBINED_COUNTETHTOOL_A_RINGS_TCP_DATA_SPLITETHTOOL_A_RINGS_TX_PUSH_BUF_LENETHTOOL_A_RINGS_TX_PUSH_BUF_LEN_MAXETHTOOL_A_RINGS_HDS_THRESH_MAXETHTOOL_A_LINKSTATE_EXT_SUBSTATEETHTOOL_A_LINKSTATE_EXT_DOWN_CNTETHTOOL_A_LINKMODES_MASTER_SLAVE_CFGETHTOOL_A_LINKMODES_MASTER_SLAVE_STATEETHTOOL_A_LINKMODES_RATE_MATCHINGETHTOOL_A_LINKINFO_TP_MDIX_CTRLETHTOOL_A_LINKINFO_TRANSCEIVERCMIS module is not in ModuleReady stateLarge number of physical errorsPCS did not acquire block lockKR Link partner did not set receiver readyNo partner detected during force modeETHTOOL_MSG_LINKINFO_GET_REPLYETHTOOL_MSG_LINKMODES_GET_REPLYETHTOOL_MSG_LINKSTATE_GET_REPLYETHTOOL_MSG_FEATURES_GET_REPLYETHTOOL_MSG_FEATURES_SET_REPLYETHTOOL_MSG_PRIVFLAGS_GET_REPLYETHTOOL_MSG_CHANNELS_GET_REPLYETHTOOL_MSG_COALESCE_GET_REPLYETHTOOL_MSG_CABLE_TEST_TDR_NTFETHTOOL_MSG_TUNNEL_INFO_GET_REPLYETHTOOL_MSG_MODULE_EEPROM_GET_REPLYETHTOOL_MSG_PHC_VCLOCKS_GET_REPLYETHTOOL_MSG_PLCA_GET_CFG_REPLYETHTOOL_MSG_PLCA_GET_STATUS_REPLYETHTOOL_MSG_MODULE_FW_FLASH_NTFETHTOOL_MSG_TSCONFIG_GET_REPLYETHTOOL_MSG_TSCONFIG_SET_REPLYETHTOOL_MSG_CABLE_TEST_TDR_ACTETHTOOL_MSG_MODULE_FW_FLASH_ACTdata [bytes] = %u dwords [bytes] %u UNKNOWN[%s]%-*s[0x%04x]: 0x%08x [08:08] OB_CPL_CTO: 0x%02x [14:14] OB_AR_UF: 0x%02x [15:15] IB_TAG_ERR: 0x%02x [16:16] IB_CPL_UF: 0x%02x [17:17] IB_NP_OF: 0x%02x [07:00] IP_EDMA: 0x%05x [00:00] BUS_MASTER: 0x%02x [01:01] MEM_SPACE: 0x%02x [02:02] RCB: 0x%02x [03:03] IDO_REQ_EN: 0x%02x [04:04] IDO_CPL_EN: 0x%02x [05:05] PM_STS: 0x%02x [07:07] WAKE: 0x%02x [03:03] CORE_RST_N: 0x%02x [01:01] VPD: 0x%02x RADM_TRGT1_HDR_ERR_COREOUTPUT [09:09] %s: 0x%02x [10:10] %s: 0x%02x ERR_DETECT_RADM_TRGT1_DATA [11:11] %s: 0x%02x ERR_MULTPL_RADM_TRGT1_DATA [12:12] %s: 0x%02x [13:13] %s: 0x%02x [14:14] %s: 0x%02x [15:15] %s: 0x%02x [16:16] %s: 0x%02x ERR_DETECT_EDMA2RAM_ADDRA [17:17] %s: 0x%02x ERR_MULTPL_EDMA2RAM_ADDRA [18:18] %s: 0x%02x ERR_DETECT_EDMA2RAM_ADDRB [19:19] %s: 0x%02x ERR_MULTPL_EDMA2RAM_ADDRB [20:20] %s: 0x%02x [10:03] PBUS_NUM: 0x%05x [16:16] IDO_REQ_EN: 0x%02x [17:17] IDO_CPL_EN: 0x%02x [28:28] AW_ENB: 0x%02x [29:29] AR_RCB: 0x%02x [07:05] PM_DSTATE: 0x%02x [09:09] PM_STS: 0x%02x [23:23] WAKE: 0x%02x [04:04] CORE_RST_N: 0x%02x [08:01] %s: 0x%05x [20:09] %s: 0x%05x [22:21] %s: 0x%02x [15:00] DATA: 0x%05x [02:00] AW_TQM_TC: 0x%02x [05:03] AW_RQM_TC: 0x%02x [08:06] AW_RDE_TC: 0x%02x [18:18] AW_IP_BME: 0x%02x [19:19] AW_FLUSH: 0x%02x [02:00] AR_TQM_TC: 0x%02x [05:03] AR_RQM_TC: 0x%02x [08:06] AR_TDE_TC: 0x%02x [18:18] AR_IP_BME: 0x%02x [19:19] AR_FLUSH: 0x%02x [20:20] AR_SLV_ERR: 0x%02x [21:21] AR_CPL_IP: 0x%02x [02:00] AW_TC: 0x%02x [05:03] AW_ATTR: 0x%02x [06:06] AW_TH: 0x%02x [02:00] AR_TC: 0x%02x [05:03] AR_ATTR: 0x%02x [06:06] AR_TH: 0x%02x [23:16] HDR: 0x%05x [11:00] DATA: 0x%05x [07:00] HDR_THRESH: 0x%05x [08:00] MAX_TAGS: 0x%05x [07:00] TAG: 0x%05x [11:00] HDR_CRDTS: 0x%05x [11:00] HDR_CRED: 0x%05x [27:12] DATA_CRED: 0x%05x [08:00] HDR_CRED: 0x%05x [22:09] DATA_CRED: 0x%05x [03:00] CNT: 0x%05x [00:00] POP: 0x%02x FBNIC_PUL_USER_IB_DURGA_CPLFBNIC_QUEUE_TWQ_CTL [00:00] RESET: 0x%02x [01:01] ENABLE: 0x%02x FBNIC_QUEUE_TWQ_PTRS [15:00] TAIL_PTR: 0x%05x [31:16] HEAD_PTR: 0x%05x FBNIC_QUEUE_TWQ_STS0FBNIC_QUEUE_TWQ_STS1FBNIC_QUEUE_TWQ_SIZE [03:00] SIZE: 0x%02x FBNIC_QUEUE_TWQ_ERR_INTR_STS [05:02] TWD_ERRS: 0x%02x FBNIC_QUEUE_TWQ_BASE_ADDR_L [31:07] ADDR: 0x%08x FBNIC_QUEUE_TWQ_BASE_ADDR_HFBNIC_QUEUE_TQS_ERR_INTR_STS [03:00] TWD_ERRS: 0x%02x FBNIC_QUEUE_TDE_ERR_INTR_STSFBNIC_QUEUE_TQS_DWRR_ARB_CTL [11:00] QUANTUM: 0x%05x FBNIC_QUEUE_TDE_DMA_PTR [15:00] TWD_PTR: 0x%05x FBNIC_QUEUE_TWQ_PKT_CNTFBNIC_QUEUE_TWQ_ERR_CNTFBNIC_QUEUE_TWQ0_BYTES_LFBNIC_QUEUE_TWQ0_BYTES_HFBNIC_QUEUE_TDE_T0_CMPL_CNTFBNIC_QUEUE_TDE_TYPE1_CMPL [15:00] HEAD_PTR: 0x%05x [31:16] TAIL_PTR: 0x%05x [00:00] STATUS: 0x%08x [13:00] TCQ_TMR: 0x%05x [14:00] TWD_CNT0: 0x%05x [30:16] TWD_CNT1: 0x%05x [03:00] SIZE: 0x%08x [30:30] ENABLE_PPQ: 0x%02x [30:29] DROP_MODE: 0x%02x [05:02] PAD_BYTES: 0x%08x [30:16] RCD_CNT: 0x%05x [13:00] RCQ_TMR: 0x%05x FBNIC_SIG_MAC_IN0: 0x%08x FBNIC_SIG_MAC1: 0x%08x FBNIC_SIG_MAC2: 0x%08x FBNIC_SIG_MAC3: 0x%08x FBNIC_SIG_MAC4: 0x%08x FBNIC_SIG_MAC5: 0x%08x FBNIC_SIG_MAC6: 0x%08x FBNIC_SIG_PCS_IN0: 0x%08x [01:00] PACER_10G: 0x%02x [16:16] SD_100G: 0x%02x [18:17] SD_8X: 0x%02x [20:19] SD_N2: 0x%02x FBNIC_SIG_PCS_OUT0: 0x%08x [25:25] PCS_HI_BER: 0x%02x FBNIC_SIG_PCS_OUT1: 0x%08x FBNIC_SIG_ANEG0: 0x%08x FBNIC_SIG_ANEG1: 0x%08x [00:00] COMPHY_INT: 0x%02x [01:01] FF_TX_OVR: 0x%02x [02:02] LOC_FAULT: 0x%02x [03:03] REM_FAULT: 0x%02x [04:04] LI_FAULT: 0x%02x [05:05] REG_LOWP: 0x%02x FBNIC_SIG_PCS_OUT2: 0x%08x FBNIC_SIG_LED: 0x%08x [03:03] BLUE_MASK: 0x%02x [04:04] AMBER_MASK: 0x%02x FBNIC_SIG_LED_RATE: 0x%08x FBNIC_SIG_PCS_IN1: 0x%08x [03:00] FEC91_ENA: 0x%02x [11:08] KP_MODE_IN: 0x%02x [27:24] FEC_ENA: 0x%02x FBNIC_SIG_SPARE_REG0: 0x%08x FBNIC_SIG_SPARE_REG1: 0x%08x FBNIC_SIG_SPARE_REG2: 0x%08x FBNIC_SIG_MEM_%s: 0x%08x [00:00] TXD: 0x%02x [01:01] SDTM_LANE0: 0x%02x [02:02] SDTM_LANE1: 0x%02x [07:07] F91DM_MEM0: 0x%02x [08:08] F91DM_MEM1: 0x%02x [09:09] F91RO_MEM0: 0x%02x [10:10] F91RO_MEM1: 0x%02x [11:11] F91RO_MEM2: 0x%02x [12:12] F91RO_MEM3: 0x%02x %s: Unknown! (%d) %s: %s Symmetric Receive-onlyTransmit-only %s(none)ifname PHYAD: %u transceiverTransceiverlink-detectedlink-state (%s (%u, %usqi SQI: %usqi-max/%u link-down-events Link Down Events: %u , %s Link detected: %s PLCA support: OPEN Alliance v%u.%u %1$u.%1$uopen-alliance-vnon-standardplca-supportPLCA status: %ssendinggenetlinkrtnetlink%s %s packet (%u bytes): msg length %u noop malformed errno=%d done overrun type %u ethool cmd %u genl-ctrl %s [%u] family=%u type=0x%04x ifindex=%d flags=0x%x change=0x%x and attributenetlink %s: %s (offset %u)netlink erroroffending message%s: -sethtoolcurrent-message-level %*ssupported-portsSupported link modes: supported-link-modessupported-pause-frame-useSupported pause frame use: supports-auto-negotiationSupported FEC modes: supported-fec-modesAdvertised link modes: advertised-link-modesadvertised-pause-frame-useAdvertised pause frame use: advertised-auto-negotiationAdvertised FEC modes: advertised-fec-modes Speed: Unknown! Speed: %uMb/s lanes Lanes: %u master-slave-cfgmaster-slave cfgmaster-slave-statusmaster-slave statuspreferred-masterpreferred-slaveforced-masterforced-slavetpdaNL_ATTR_TYPE_INVALIDNL_ATTR_TYPE_FLAGNL_ATTR_TYPE_U8NL_ATTR_TYPE_U16NL_ATTR_TYPE_U32NL_ATTR_TYPE_U64NL_ATTR_TYPE_S8NL_ATTR_TYPE_S16NL_ATTR_TYPE_S32NL_ATTR_TYPE_S64NL_ATTR_TYPE_BINARYNL_ATTR_TYPE_STRINGNL_ATTR_TYPE_NUL_STRINGNL_ATTR_TYPE_NESTEDNL_ATTR_TYPE_NESTED_ARRAYNL_ATTR_TYPE_BITFIELD32ETHTOOL_A_STRING_UNSPECETHTOOL_A_STRING_INDEXETHTOOL_A_STRING_VALUENL_POLICY_TYPE_ATTR_UNSPECNL_POLICY_TYPE_ATTR_TYPENL_POLICY_TYPE_ATTR_PADNL_POLICY_TYPE_ATTR_MASKETHTOOL_A_BITSET_BIT_UNSPECETHTOOL_A_BITSET_BIT_INDEXETHTOOL_A_BITSET_BIT_NAMEETHTOOL_A_BITSET_BIT_VALUEETHTOOL_A_STRINGS_UNSPECETHTOOL_A_STRINGS_STRINGCTRL_ATTR_POLICY_UNSPECCTRL_ATTR_POLICY_DOCTRL_ATTR_POLICY_DUMPCTRL_ATTR_MCAST_GRP_UNSPECCTRL_ATTR_MCAST_GRP_NAMECTRL_ATTR_MCAST_GRP_IDCTRL_ATTR_OP_UNSPECCTRL_ATTR_OP_IDCTRL_ATTR_OP_FLAGSETHTOOL_A_CABLE_PULSE_UNSPECETHTOOL_A_CABLE_PULSE_mVETHTOOL_A_CABLE_AMPLITUDE_mVETHTOOL_A_CABLE_STEP_UNSPECETHTOOL_A_CABLE_RESULT_UNSPECETHTOOL_A_CABLE_RESULT_PAIRETHTOOL_A_CABLE_RESULT_CODEETHTOOL_A_CABLE_RESULT_SRCETHTOOL_A_STATS_GRP_HIST_VALETHTOOL_A_IRQ_MODERATION_USECETHTOOL_A_IRQ_MODERATION_PKTSETHTOOL_A_BITSET_BITS_UNSPECETHTOOL_A_BITSET_BITS_BITETHTOOL_A_STRINGSET_UNSPECETHTOOL_A_STRINGSET_IDETHTOOL_A_STRINGSET_COUNTETHTOOL_A_STRINGSET_STRINGSETHTOOL_A_CABLE_TDR_NEST_STEPETHTOOL_A_CABLE_NEST_UNSPECETHTOOL_A_CABLE_NEST_RESULTETHTOOL_A_MM_STAT_UNSPECETHTOOL_A_MM_STAT_PADETHTOOL_A_MM_STAT_SMD_ERRORSETHTOOL_A_MM_STAT_HOLD_COUNTETHTOOL_A_STATS_GRP_UNSPECETHTOOL_A_STATS_GRP_PADETHTOOL_A_STATS_GRP_IDETHTOOL_A_STATS_GRP_SS_IDETHTOOL_A_STATS_GRP_STATETHTOOL_A_STATS_GRP_HIST_RXETHTOOL_A_STATS_GRP_HIST_TXETHTOOL_A_FEC_STAT_UNSPECETHTOOL_A_FEC_STAT_PADETHTOOL_A_FEC_STAT_CORRECTEDETHTOOL_A_FEC_STAT_UNCORRETHTOOL_A_FEC_STAT_CORR_BITSETHTOOL_A_TUNNEL_UDP_UNSPECETHTOOL_A_TUNNEL_UDP_TABLEETHTOOL_A_TS_STAT_UNSPECETHTOOL_A_TS_STAT_TX_PKTSETHTOOL_A_TS_STAT_TX_LOSTETHTOOL_A_TS_STAT_TX_ERRETHTOOL_A_PAUSE_STAT_PADETHTOOL_A_PROFILE_UNSPECRATE_MATCH_NONERATE_MATCH_PAUSERATE_MATCH_CRSRATE_MATCH_OPEN_LOOPETHTOOL_A_BITSET_UNSPECETHTOOL_A_BITSET_NOMASKETHTOOL_A_BITSET_SIZEETHTOOL_A_BITSET_BITSETHTOOL_A_BITSET_VALUEETHTOOL_A_BITSET_MASKETHTOOL_A_STRINGSETS_UNSPECETHTOOL_A_HEADER_UNSPECETHTOOL_A_HEADER_DEV_INDEXETHTOOL_A_HEADER_DEV_NAMEETHTOOL_A_HEADER_FLAGSCTRL_ATTR_UNSPECCTRL_ATTR_FAMILY_IDCTRL_ATTR_FAMILY_NAMECTRL_ATTR_VERSIONCTRL_ATTR_HDRSIZECTRL_ATTR_MAXATTRCTRL_ATTR_OPSCTRL_ATTR_MCAST_GROUPSCTRL_ATTR_POLICYCTRL_ATTR_OP_POLICYCTRL_ATTR_OPETHTOOL_A_CABLE_TEST_NTF_NESTETHTOOL_A_TSCONFIG_UNSPECETHTOOL_A_TSCONFIG_HEADERETHTOOL_A_TSCONFIG_TX_TYPESETHTOOL_A_TSCONFIG_RX_FILTERSETHTOOL_A_PHY_UNSPECETHTOOL_A_PHY_HEADERETHTOOL_A_PHY_INDEXETHTOOL_A_PHY_DRVNAMEETHTOOL_A_PHY_NAMEETHTOOL_A_PHY_UPSTREAM_TYPEETHTOOL_A_PHY_UPSTREAM_INDEXETHTOOL_A_MM_UNSPECETHTOOL_A_MM_HEADERETHTOOL_A_MM_PMAC_ENABLEDETHTOOL_A_MM_TX_ENABLEDETHTOOL_A_MM_TX_ACTIVEETHTOOL_A_MM_TX_MIN_FRAG_SIZEETHTOOL_A_MM_RX_MIN_FRAG_SIZEETHTOOL_A_MM_VERIFY_ENABLEDETHTOOL_A_MM_VERIFY_STATUSETHTOOL_A_MM_VERIFY_TIMEETHTOOL_A_MM_MAX_VERIFY_TIMEETHTOOL_A_MM_STATSETHTOOL_A_PLCA_UNSPECETHTOOL_A_PLCA_HEADERETHTOOL_A_PLCA_VERSIONETHTOOL_A_PLCA_ENABLEDETHTOOL_A_PLCA_STATUSETHTOOL_A_PLCA_NODE_CNTETHTOOL_A_PLCA_NODE_IDETHTOOL_A_PLCA_TO_TMRETHTOOL_A_PLCA_BURST_CNTETHTOOL_A_PLCA_BURST_TMRETHTOOL_A_RSS_UNSPECETHTOOL_A_RSS_HEADERETHTOOL_A_RSS_CONTEXTETHTOOL_A_RSS_HFUNCETHTOOL_A_RSS_INDIRETHTOOL_A_RSS_HKEYETHTOOL_A_RSS_INPUT_XFRMETHTOOL_A_RSS_START_CONTEXTETHTOOL_A_PSE_UNSPECETHTOOL_A_PSE_HEADERETHTOOL_A_C33_PSE_ADMIN_STATEETHTOOL_A_C33_PSE_PW_D_STATUSETHTOOL_A_C33_PSE_PW_CLASSETHTOOL_A_C33_PSE_ACTUAL_PWETHTOOL_A_C33_PSE_EXT_STATEETHTOOL_A_MODULE_UNSPECETHTOOL_A_MODULE_HEADERETHTOOL_A_MODULE_POWER_MODEETHTOOL_A_PHC_VCLOCKS_UNSPECETHTOOL_A_PHC_VCLOCKS_HEADERETHTOOL_A_PHC_VCLOCKS_NUMETHTOOL_A_PHC_VCLOCKS_INDEXETHTOOL_A_STATS_UNSPECETHTOOL_A_STATS_PADETHTOOL_A_STATS_HEADERETHTOOL_A_STATS_GROUPSETHTOOL_A_STATS_GRPETHTOOL_A_STATS_SRCETHTOOL_A_MODULE_EEPROM_PAGEETHTOOL_A_MODULE_EEPROM_BANKETHTOOL_A_MODULE_EEPROM_DATAETHTOOL_A_FEC_UNSPECETHTOOL_A_FEC_HEADERETHTOOL_A_FEC_MODESETHTOOL_A_FEC_AUTOETHTOOL_A_FEC_ACTIVEETHTOOL_A_FEC_STATSETHTOOL_A_TUNNEL_INFO_UNSPECETHTOOL_A_TUNNEL_INFO_HEADERETHTOOL_A_CABLE_TEST_TDR_CFGETHTOOL_A_CABLE_TEST_UNSPECETHTOOL_A_CABLE_TEST_HEADERETHTOOL_A_TSINFO_UNSPECETHTOOL_A_TSINFO_HEADERETHTOOL_A_TSINFO_TIMESTAMPINGETHTOOL_A_TSINFO_TX_TYPESETHTOOL_A_TSINFO_RX_FILTERSETHTOOL_A_TSINFO_PHC_INDEXETHTOOL_A_TSINFO_STATSETHTOOL_A_EEE_UNSPECETHTOOL_A_EEE_HEADERETHTOOL_A_EEE_MODES_OURSETHTOOL_A_EEE_MODES_PEERETHTOOL_A_EEE_ACTIVEETHTOOL_A_EEE_ENABLEDETHTOOL_A_EEE_TX_LPI_ENABLEDETHTOOL_A_EEE_TX_LPI_TIMERETHTOOL_A_PAUSE_UNSPECETHTOOL_A_PAUSE_HEADERETHTOOL_A_PAUSE_AUTONEGETHTOOL_A_PAUSE_RXETHTOOL_A_PAUSE_TXETHTOOL_A_PAUSE_STATSETHTOOL_A_PAUSE_STATS_SRCETHTOOL_A_COALESCE_UNSPECETHTOOL_A_COALESCE_HEADERETHTOOL_A_COALESCE_RX_USECSETHTOOL_A_COALESCE_TX_USECSETHTOOL_A_COALESCE_RX_PROFILEETHTOOL_A_COALESCE_TX_PROFILEETHTOOL_A_CHANNELS_UNSPECETHTOOL_A_CHANNELS_HEADERETHTOOL_A_CHANNELS_RX_MAXETHTOOL_A_CHANNELS_TX_MAXETHTOOL_A_CHANNELS_OTHER_MAXETHTOOL_A_CHANNELS_RX_COUNTETHTOOL_A_CHANNELS_TX_COUNTETHTOOL_A_RINGS_UNSPECETHTOOL_A_RINGS_HEADERETHTOOL_A_RINGS_RX_MAXETHTOOL_A_RINGS_RX_MINI_MAXETHTOOL_A_RINGS_RX_JUMBO_MAXETHTOOL_A_RINGS_TX_MAXETHTOOL_A_RINGS_RXETHTOOL_A_RINGS_RX_MINIETHTOOL_A_RINGS_RX_JUMBOETHTOOL_A_RINGS_TXETHTOOL_A_RINGS_RX_BUF_LENETHTOOL_A_RINGS_CQE_SIZEETHTOOL_A_RINGS_TX_PUSHETHTOOL_A_RINGS_RX_PUSHETHTOOL_A_RINGS_HDS_THRESHETHTOOL_A_PRIVFLAGS_UNSPECETHTOOL_A_PRIVFLAGS_HEADERETHTOOL_A_PRIVFLAGS_FLAGSETHTOOL_A_FEATURES_UNSPECETHTOOL_A_FEATURES_HEADERETHTOOL_A_FEATURES_HWETHTOOL_A_FEATURES_WANTEDETHTOOL_A_FEATURES_ACTIVEETHTOOL_A_FEATURES_NOCHANGEETHTOOL_A_WOL_UNSPECETHTOOL_A_WOL_HEADERETHTOOL_A_WOL_MODESETHTOOL_A_WOL_SOPASSETHTOOL_A_DEBUG_UNSPECETHTOOL_A_DEBUG_HEADERETHTOOL_A_DEBUG_MSGMASKETHTOOL_A_LINKSTATE_UNSPECETHTOOL_A_LINKSTATE_HEADERETHTOOL_A_LINKSTATE_LINKETHTOOL_A_LINKSTATE_SQIETHTOOL_A_LINKSTATE_SQI_MAXETHTOOL_A_LINKSTATE_EXT_STATEETHTOOL_A_LINKMODES_UNSPECETHTOOL_A_LINKMODES_HEADERETHTOOL_A_LINKMODES_AUTONEGETHTOOL_A_LINKMODES_OURSETHTOOL_A_LINKMODES_PEERETHTOOL_A_LINKMODES_SPEEDETHTOOL_A_LINKMODES_DUPLEXETHTOOL_A_LINKMODES_LANESETHTOOL_A_LINKINFO_UNSPECETHTOOL_A_LINKINFO_HEADERETHTOOL_A_LINKINFO_PORTETHTOOL_A_LINKINFO_PHYADDRETHTOOL_A_LINKINFO_TP_MDIXETHTOOL_A_STRSET_UNSPECETHTOOL_A_STRSET_HEADERETHTOOL_A_STRSET_STRINGSETSETHTOOL_A_STRSET_COUNTS_ONLYIFLA_UNSPECIFLA_ADDRESSIFLA_BROADCASTIFLA_IFNAMEIFLA_MTUIFLA_LINKIFLA_QDISCIFLA_STATSIFLA_COSTIFLA_PRIORITYIFLA_MASTERIFLA_WIRELESSIFLA_PROTINFOIFLA_TXQLENIFLA_MAPIFLA_WEIGHTIFLA_OPERSTATEIFLA_LINKMODEIFLA_LINKINFOIFLA_NET_NS_PIDIFLA_IFALIASIFLA_NUM_VFIFLA_VFINFO_LISTIFLA_STATS64IFLA_VF_PORTSIFLA_PORT_SELFIFLA_AF_SPECIFLA_GROUPIFLA_NET_NS_FDIFLA_EXT_MASKIFLA_PROMISCUITYIFLA_NUM_TX_QUEUESIFLA_NUM_RX_QUEUESIFLA_CARRIERIFLA_PHYS_PORT_IDIFLA_CARRIER_CHANGESIFLA_PHYS_SWITCH_IDIFLA_LINK_NETNSIDIFLA_PHYS_PORT_NAMEIFLA_PROTO_DOWNIFLA_GSO_MAX_SEGSIFLA_GSO_MAX_SIZEIFLA_PADIFLA_XDPIFLA_EVENTIFLA_NEW_NETNSIDIFLA_IF_NETNSIDIFLA_CARRIER_UP_COUNTIFLA_CARRIER_DOWN_COUNTIFLA_NEW_IFINDEXIFLA_MIN_MTUIFLA_MAX_MTUIFLA_PROP_LISTIFLA_ALT_IFNAMEIFLA_PERM_ADDRESScf_tx_fifo_thrsldcf_rx_fifo_thrsldcf_cfg_fifo_thrsldcf_intrpt_mskcf_intrpt_statcf_intrpt_clrtx_bus_err_addrrx_bus_err_addrmax_frame_lendebug_st_mchfifo_curr_statusfifo_his_statuscf_cff_data_numcf_tx_pauserx_cff_addrrx_buf_sizebus_ctrlrx_ctrlrx_pkt_modedbg_st0dbg_st1dbg_st2bus_rst_encf_ind_txint_mskcf_ind_txint_statcf_ind_txint_clrcf_ind_rxint_mskcf_ind_rxint_statcf_ind_rxint_clrduplex_typefd_fc_typefc_tx_timerfd_fc_addr_lowfd_fc_addr_highmax_frm_sizeport_modeport_enpause_enan_neg_statetransmit_ctrlrec_filt_ctrlline_loop_backcf_crc_stripmode_change_enloop_regrecv_controlvlan_codestation_addr_low_0station_addr_high_0station_addr_low_1station_addr_high_1station_addr_low_2station_addr_high_2station_addr_low_3station_addr_high_3station_addr_low_4station_addr_high_4station_addr_low_5station_addr_high_5command_regaddr_regwdata_regrdata_regsta_regevent_reqmac_idphy_addrmac_addr_lmac_addr_huc_max_nummdio_freqmax_mtumin_mtutx_fifo_numrx_fifo_numvlan_layersUnsupported cableCable test failureUnsupported rateSerdes reference clock lostSerdes ALOSPCS did not acquire AM lockPCS did not get align_statusFC FEC is not lockedRS FEC is not lockedKR frame lock not acquiredKR link inhibit timeoutRemote side is not ready yetNo partner detectedAck not receivedNext page exchange failedFEC mismatch during overrideNo HCDLink training failureLogical mismatchBad signal integrityNo cableCable issueEEPROM issueCalibration failurePower budget exceededOverheatModuleTwisted PairFIBREDirect Attach CopperOtherresolution errorpreferred masterpreferred slaveforced masterforced slaveCTRL_CMD_UNSPECCTRL_CMD_NEWFAMILYCTRL_CMD_DELFAMILYCTRL_CMD_GETFAMILYCTRL_CMD_NEWOPSCTRL_CMD_DELOPSCTRL_CMD_GETOPSCTRL_CMD_NEWMCAST_GRPCTRL_CMD_DELMCAST_GRPCTRL_CMD_GETMCAST_GRPCTRL_CMD_GETPOLICYETHTOOL_MSG_KERNEL_NONEETHTOOL_MSG_STRSET_GET_REPLYETHTOOL_MSG_LINKINFO_NTFETHTOOL_MSG_LINKMODES_NTFETHTOOL_MSG_DEBUG_GET_REPLYETHTOOL_MSG_DEBUG_NTFETHTOOL_MSG_WOL_GET_REPLYETHTOOL_MSG_WOL_NTFETHTOOL_MSG_FEATURES_NTFETHTOOL_MSG_PRIVFLAGS_NTFETHTOOL_MSG_RINGS_GET_REPLYETHTOOL_MSG_RINGS_NTFETHTOOL_MSG_CHANNELS_NTFETHTOOL_MSG_COALESCE_NTFETHTOOL_MSG_PAUSE_GET_REPLYETHTOOL_MSG_PAUSE_NTFETHTOOL_MSG_EEE_GET_REPLYETHTOOL_MSG_EEE_NTFETHTOOL_MSG_TSINFO_GET_REPLYETHTOOL_MSG_CABLE_TEST_NTFETHTOOL_MSG_FEC_GET_REPLYETHTOOL_MSG_FEC_NTFETHTOOL_MSG_STATS_GET_REPLYETHTOOL_MSG_MODULE_GET_REPLYETHTOOL_MSG_MODULE_NTFETHTOOL_MSG_PSE_GET_REPLYETHTOOL_MSG_RSS_GET_REPLYETHTOOL_MSG_PLCA_NTFETHTOOL_MSG_MM_GET_REPLYETHTOOL_MSG_MM_NTFETHTOOL_MSG_PHY_GET_REPLYETHTOOL_MSG_PHY_NTFETHTOOL_MSG_USER_NONEETHTOOL_MSG_STRSET_GETETHTOOL_MSG_LINKINFO_GETETHTOOL_MSG_LINKINFO_SETETHTOOL_MSG_LINKMODES_GETETHTOOL_MSG_LINKMODES_SETETHTOOL_MSG_LINKSTATE_GETETHTOOL_MSG_DEBUG_GETETHTOOL_MSG_DEBUG_SETETHTOOL_MSG_WOL_GETETHTOOL_MSG_WOL_SETETHTOOL_MSG_FEATURES_GETETHTOOL_MSG_FEATURES_SETETHTOOL_MSG_PRIVFLAGS_GETETHTOOL_MSG_PRIVFLAGS_SETETHTOOL_MSG_RINGS_GETETHTOOL_MSG_RINGS_SETETHTOOL_MSG_CHANNELS_GETETHTOOL_MSG_CHANNELS_SETETHTOOL_MSG_COALESCE_GETETHTOOL_MSG_COALESCE_SETETHTOOL_MSG_PAUSE_GETETHTOOL_MSG_PAUSE_SETETHTOOL_MSG_EEE_GETETHTOOL_MSG_EEE_SETETHTOOL_MSG_TSINFO_GETETHTOOL_MSG_CABLE_TEST_ACTETHTOOL_MSG_TUNNEL_INFO_GETETHTOOL_MSG_FEC_GETETHTOOL_MSG_FEC_SETETHTOOL_MSG_MODULE_EEPROM_GETETHTOOL_MSG_STATS_GETETHTOOL_MSG_PHC_VCLOCKS_GETETHTOOL_MSG_MODULE_GETETHTOOL_MSG_MODULE_SETETHTOOL_MSG_PSE_GETETHTOOL_MSG_PSE_SETETHTOOL_MSG_RSS_GETETHTOOL_MSG_PLCA_GET_CFGETHTOOL_MSG_PLCA_SET_CFGETHTOOL_MSG_PLCA_GET_STATUSETHTOOL_MSG_MM_GETETHTOOL_MSG_MM_SETETHTOOL_MSG_PHY_GETETHTOOL_MSG_TSCONFIG_GETETHTOOL_MSG_TSCONFIG_SETRTM_NEWLINKRTM_DELLINKRTM_GETLINKRTM_SETLINKMDIOGMACPCUm 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,Np/X2TvCl9b:c@@@@@@pppppp0000````\~))D)D)A0A0f//f//..--D)D)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)9--9--<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)},D)&,D)},D)&,D)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)+r+U+8+++***<)<)<)<)<)<)<)+r+U+8+++***<)<)<)<)<)<)<)2D)2114D)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)w4S4<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)433D)3a3?<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)?D)?>>=D)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)x=T=<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)<)|6|6|6>=|6|6<=l<;|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6|6;;l;|6|6|6|6|6666|6666nIMMIMMxMgeAh$hghggggg:  dd' ''' N N@@@@aaaPPP''''' PPPPP@ @ @ @ @ d@ @ @ @ @ dd 5 5 5 5 5 5     @ @ @ @ @ @ 5 5 5 5 5 5  ethtool (%s): preciseapprox bit%u Permanent address: not setPermanent address of %s:Pre-set maximums: rx-maxRX: %s%u %sn/a tx-maxTX: other-maxOther: Current hardware settings: combined-maxCombined: n/astats-block-usecs: sample-interval: pkt-rate-low: pkt-rate-high: rx-usecs: rx-frames: rx-usecs-irq: rx-frames-irq: tx-usecs: tx-frames: tx-usecs-irq: tx-frames-irq: rx-usecs-low: rx-frame-lowrx-frame-low: tx-usecs-low: tx-frame-lowtx-frame-low: rx-usecs-high: rx-frame-highrx-frame-high: tx-usecs-high: tx-frame-hightx-frame-high: cqe-mode-rxcqe-mode-txtx-aggr-max-bytestx-aggr-max-bytes: tx-aggr-max-framestx-aggr-max-frames: tx-aggr-time-usecstx-aggr-time-usecs: CQE mode RX: %s Adaptive RX: %s fixednullrequested%s [requested %s]%s [not requested]RX: rx-mini-maxRX Mini: rx-jumbo-maxRX Jumbo: TX: tx-push-buff-max-lenTX push buff len: hds-thresh-maxHDS thresh: rx-buf-lenRX Buf Len: cqe-sizeCQE Size: tx-pushrx-pushtx-push-buf-lenTCP data split: %s tcp-data-splitunknown(%d) hds-threshRX Push: %s TX Push: %s negotiatedTX negotiated: %s RX negotiated: %s autonegotiateStatistics: %s: %%lu TX: %s RX: %s Autonegotiate: %s inactiveEEE settings for %s: enabled - %s Tx LPI: %u (us) Supported EEE link modes: supported-eee-link-modesAdvertised EEE link modes: advertised-eee-link-modes BIT%u %s: %lu total Lane %d: %lu -L-C-a-A===>%s%*s%s%s%*s[%u]0x%08x%lx%ld"%.*s" %*sPrecise (IEEE 1588 quality)Approximateunsupportedhwtstamp-provider-indexhwtstamp-provider-qualifierCapabilities noneHardware Receive Filter Modesaggregatepmaccorrected_blocksuncorrectable_blockscorrected_bitstx_pktstx_lost--srcethtool (%s): invalid value '%s' for parameter '%s' ethtool (%s): too few arguments for parameter '%s' (expected %u) ethtool (%s): invalid value '%s' of parameter '%s' ethtool (%s): internal error parsing '%s' ethtool (%s): flag '%s' for parameter '%s' is not followed by 'on' or 'off' ethtool (%s): invalid char '%c' in '%s' for parameter '%s' ethtool: unexpected parameter '%s' warning: unexpected reply message type %u warning: unexpected message for device %s malformed diff info from kernel malformed netlink message (statistic) internal error - malformed label Malformed response from kernel Link partner advertised EEE link modes: link-partner-advertised-eee-link-modesethtool (%s): duplicate parameter '%s' ethtool (%s): no value for parameter '%s' ethtool (%s): parameter '%s' requires %u words ethtool (%s): unknown parameter '%s' ethtool (--set-eee): parameters missing ethtool (--set-fec): parameters missing ethtool: bad_attr inside an attribute (offset %d) Hardware timestamp provider index: %u Hardware timestamp provider qualifier: %s Hardware Transmit Timestamp Modesd)d)D,,++l,,,4. .---l-L-4-,d)d)|+|+C?Underload statePort is not connectedNon-existing port numberUndefined portInternal hardware faultUnknown port statusHost crash turn offHost crash force shutdownConfiguration changeOver temperature detectedDisable pin activeDetection in processConnection check errorMain supply voltage is highMain supply voltage is lowOverload stateShort condition was detected-SModule parameters for %s: power-mode-policy: %s power-mode-policypower-mode: %s power-modeINITIALVERIFYINGSUCCEEDEDFAILEDDISABLEDpmac-enabledtx-enabledtx-activetx-min-frag-sizeTX minimum fragment size: rx-min-frag-sizeRX minimum fragment size: verify-enabledVerify time: max-verify-timeMax verify time: Verification status: %s verify-statusFailed to print stats: %d Verify enabled: %s TX active: %s TX enabled: %s pMAC enabled: %s Pair APair BPair CPair DUnexpected pairOpen CircuitShort within PairShort to another pairTDRALCDcode %s, source: %s%s, fault length: %0.2fmsearchingdelivering powersleepidleotherfaultGroup of mr_mps_valid statesGroup of mr_pse_enable statesGroup of option_detect_tedGroup of ovld_detected statesPSE attributes for %s: PoDL PSE Admin State: %s podl-pse-admin-statec33-pse-admin-statec33-pse-extended-statec33-pse-extended-substatec33-pse-power-classc33-pse-actual-powerc33-pse-available-power-limitc33-pse-power-limit-ranges range: range min %u max %u PHY for %s: phy_indexDriver name: %s drvnamePHY device name: %s Downstream SFP bus name: %s downstream_sfp_nameUpstream type: %s upstream_typeupstream_indexUpstream PHY index: Upstream SFP name: %s upstream_sfp_nameStatus message: %s Progress: %lu% amplitudeAmplitude %4d pulseTDR Pulse %dmV firstStep configuration: %.2f-last%.2f meters stepin %.2fm steps %s-%s-etherStatsPkts%uto%uOctets: %llu %utoMaxOctets: %llu Standard stats for %s: %s-%s: rx-pktsNtoMtx-pktsNtoM bit%ucoordinatorunconfiguredfollowerPLCA settings for %s: Enabled: local node ID: %u (%s) Node count: (ignored) TO timer: %u BT Burst count: Burst timer: PLCA status of %s: Status: Cannot start cable test UDP port table %d: Size: %d Types: No entries Entries (%d): port %d, %s Tunnel information for %s: Hardware Receive Filter ModeHardware FlagsCannot start cable test TDR %-41s : None %-41s : [ %s%cInvalid boolean %s [%u] -mFailed to read Page A2h. --set-hwtstamp-cfghigh_alarm_thresholdlow_alarm_thresholdhigh_warning_thresholdlow_warning_thresholdlaser_rx_power%5u: %5urss-indirection-tablerss-hash-keyrss-hash-functionrss-hash-function-rawrss-input-transformationpodl-pse-admin-controlc33-pse-admin-controlc33-pse-avail-pw-limitnode-idnode-cntto-tmrburst-cntburst-tmrpagebanki2cMACMergeFrameAssErrorCountMACMergeFrameSmdErrorCountMACMergeFrameAssOkCountMACMergeFragCountRxMACMergeFragCountTxMACMergeHoldCount--groups--all-groupsCommunication error after force onVoltage injection into the portPower budget exceeded for the controllerConfigured port power limit exceeded controller power budgetPower request from PD exceeds port limitPower denied due to Hardware power limitMAC Merge layer state for %s: Cable test started for device %s. Cable test completed for device %s. Group of error_condition statesGroup of option_vport_lim statesGroup of pd_dll_power_type statesGroup of power_not_available statesGroup of short_detected statesPoDL PSE Power Detection Status: %s podl-pse-power-detection-statusClause 33 PSE Admin State: %s Clause 33 PSE Power Detection Status: %s c33-pse-power-detection-statusClause 33 PSE Extended State: %s Clause 33 PSE Extended Substate: %s Clause 33 PSE Power Class: %u Clause 33 PSE Actual Power: %u Clause 33 PSE Available Power Limit: %u Clause 33 PSE Power Limit Ranges: malformed netlink message (power limit range) malformed netlink message (power limit min) malformed netlink message (power limit max) Transceiver module firmware flashing started for device %s Transceiver module firmware flashing in progress for device %s Transceiver module firmware flashing completed for device %s Transceiver module firmware flashing encountered an error for device %s Cable test TDR started for device %s. Cable test TDR completed for device %s. invalid kernel response - malformed histogram entry invalid kernel response - histogram entry missing attributes invalid kernel response - bad histogram entry bounds invalid kernel response - bad statistic entry malformed netlink message (udp table) malformed netlink message (table size) Types: none (static entries)malformed netlink message (types) malformed netlink message (udp entry) malformed netlink message (port) malformed netlink message (tunnel type) Time stamping configuration for %s: Hardware Transmit Timestamp ModeHex and raw dump cannot be specified together Failed to read Upper Page 03h, driver error? ethtool (--set-module): parameters missing ethtool (--flash-module-firmware): parameters missing Cannot flash transceiver module firmware ethtool (--set-plca-cfg): parameters missing ethtool (--set-pse): parameters missing Laser bias current high alarm thresholdLaser bias current low alarm thresholdLaser bias current high warning thresholdLaser bias current low warning thresholdLaser output power high alarm thresholdLaser output power low alarm thresholdLaser output power high warning thresholdLaser output power low warning thresholdModule temperature high alarm thresholdModule temperature low alarm thresholdModule temperature high warning thresholdModule temperature low warning thresholdModule voltage high alarm thresholdModule voltage low alarm thresholdModule voltage high warning thresholdModule voltage low warning thresholdLaser rx power high alarm thresholdLaser rx power low alarm thresholdLaser rx power high warning thresholdLaser rx power low warning thresholdRX flow hash indirection table for %s with %llu RX ring(s): Autonegotiate: %s RX: %s TX: %s RX negotiated: %s TX negotiated: %s  `p@P0;-'++++;q5:::;::;5::::::;46:; ;;%;1;=;:srrrrrhrHr8rrqqqqqxqPq(qqppphpHppononnpoonlN1@ no module present, unknown, or unspecifiedmodule soldered to motherboard300 pin XBIShielded Mini Multilane HD 4Xltilane HD 8XCXP2/CXP28CDFP Style 1/Styltilane HD 4X Fanout Cableltilane HD 8X FaCDFP Style 3microQSFPQSFP-DD Double Density 8X Pluggable Transceiver (INF-8628)OSFP 8X Pluggable TransceiverDSFP Dual Small Form Factor Pluggable TransceiveQSFP+ or later with Common Management Interface Specification (CSFP-DD Double Density 2X Pluggable Transceiver wSFP+ and later w; qP  \a a `i P+P @ p 0x 0  L @!x ! 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