ACIL FM

Nama	Ukuran	Aksi
arm-gic-common.h	480 B	View DL Edit
arm-gic-v3-prio.h	1.76 MB	View DL Edit
arm-gic-v3.h	23.93 MB	View DL Edit
arm-gic-v4.h	3.8 MB	View DL Edit
arm-gic.h	5.26 MB	View DL Edit
arm-vgic-info.h	1001 B	View DL Edit
arm-vic.h	353 B	View DL Edit
chained_irq.h	931 B	View DL Edit
irq-bcm2836.h	1.89 MB	View DL Edit
irq-davinci-aintc.h	674 B	View DL Edit
irq-davinci-cp-intc.h	616 B	View DL Edit
irq-ixp4xx.h	276 B	View DL Edit
irq-madera.h	3.66 MB	View DL Edit
irq-omap-intc.h	567 B	View DL Edit
irq-partition-percpu.h	1.32 MB	View DL Edit
irq-sa11x0.h	356 B	View DL Edit
mmp.h	155 B	View DL Edit
mxs.h	221 B	View DL Edit
versatile-fpga.h	353 B	View DL Edit
xtensa-mx.h	467 B	View DL Edit
xtensa-pic.h	532 B	View DL Edit

Edit file: /usr/src/kernels/5.14.0-611.34.1.el9_7.x86_64/include/linux/irqchip/irq-bcm2836.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
 *
 * Copyright 2015 Broadcom
 */

#define LOCAL_CONTROL			0x000
#define LOCAL_PRESCALER			0x008

/*
 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
 * next 2 bits identify the CPU that the GPU FIQ goes to.
 */
#define LOCAL_GPU_ROUTING		0x00c
/* When setting bits 0-3, enables PMU interrupts on that CPU. */
#define LOCAL_PM_ROUTING_SET		0x010
/* When setting bits 0-3, disables PMU interrupts on that CPU. */
#define LOCAL_PM_ROUTING_CLR		0x014
/*
 * The low 4 bits of this are the CPU's timer IRQ enables, and the
 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
 * bits).
 */
#define LOCAL_TIMER_INT_CONTROL0	0x040
/*
 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
 * override the IRQ bits).
 */
#define LOCAL_MAILBOX_INT_CONTROL0	0x050
/*
 * The CPU's interrupt status register.  Bits are defined by the
 * LOCAL_IRQ_* bits below.
 */
#define LOCAL_IRQ_PENDING0		0x060
/* Same status bits as above, but for FIQ. */
#define LOCAL_FIQ_PENDING0		0x070
/*
 * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
 * these bits are organized by mailbox number and then CPU number.  We
 * use mailbox 0 for IPIs.  The mailbox's interrupt is raised while
 * any bit is set.
 */
#define LOCAL_MAILBOX0_SET0		0x080
#define LOCAL_MAILBOX3_SET0		0x08c
/* Mailbox write-to-clear bits. */
#define LOCAL_MAILBOX0_CLR0		0x0c0
#define LOCAL_MAILBOX3_CLR0		0x0cc

#define LOCAL_IRQ_CNTPSIRQ	0
#define LOCAL_IRQ_CNTPNSIRQ	1
#define LOCAL_IRQ_CNTHPIRQ	2
#define LOCAL_IRQ_CNTVIRQ	3
#define LOCAL_IRQ_MAILBOX0	4
#define LOCAL_IRQ_MAILBOX1	5
#define LOCAL_IRQ_MAILBOX2	6
#define LOCAL_IRQ_MAILBOX3	7
#define LOCAL_IRQ_GPU_FAST	8
#define LOCAL_IRQ_PMU_FAST	9
#define LAST_IRQ		LOCAL_IRQ_PMU_FAST

Batal